TEA1751T; TEA1751LT
GreenChip III SMPS control IC
Rev. 02 — 23 December 2009
Product data sheet
1. General description
The GreenChip III is the third generation of green Switched Mode Power Supply (SMPS)
controller ICs. The TEA1751(L)T (TEA1751T and TEA1751LT) combines a controller for
Power Factor Correction (PFC) and a flyback controller. Its high level of integration allows
the design of a cost-effective power supply with a very low number of external
components.
The special built-in green functions provide high efficiency at all power levels. This applies
to quasi-resonant operation at high power levels, quasi-resonant operation with valley
skipping, as well as to reduced frequency operation at lower power levels. At low power
levels, the PFC switches off to maintain high efficiency.
During low power conditions, the flyback controller switches to frequency reduction mode
and limits the peak current to 25 % of its maximum value. This will ensure high efficiency
at low power and good standby power performance while minimizing audible noise from
the transformer.
The TEA1751(L)T is a MultiChip Module, (MCM), containing two chips. The proprietary
high voltage BCD800 process which makes direct start-up possible from the rectified
universal mains voltage in an effective and green way. The second low voltage SIlicon On
Insulator (SIOI) is used for accurate, high speed protection functions and control.
The TEA1751(L)T enables highly efficient and reliable supplies with power requirements
up to 250 W, to be designed easily and with a minimum number of external components.
2. Features
2.1 Distinctive features
Integrated PFC and flyback controller.
Universal mains supply operation (70 V (AC) to 276 V (AC)).
Dual boost PFC with accurate maximum output voltage (NXP patented).
High level of integration, resulting in a very low external component count and a
cost-effective design.
2.2 Green features
On-chip start-up current source.
NXP Semiconductors
TEA1751T; TEA1751LT
GreenChip III SMPS control IC
2.3 PFC green features
Valley/zero voltage switching for minimum switching losses (NXP patented).
Frequency limitation to reduce switching losses.
PFC is switched off when a low load is detected at the flyback output.
2.4 Flyback green features
Valley switching for minimum switching losses (NXP patented).
Frequency reduction with fixed minimum peak current at low power operation to
maintain high efficiency at low output power levels.
2.5 Protection features
Safe restart mode for system fault conditions.
Continuous mode protection by means of demagnetization detection for both
converters (NXP patented).
UnderVoltage Protection (UVP) (foldback during overload).
Accurate OverVoltage Protection (OVP) for both converters (adjustable for flyback
converter).
Mains voltage independent OverPower Protection (OPP)
Open control loop protection for both converters. The open loop protection on the
flyback converter is latched on the TEA1751L and safe restart on the TEA1751.
IC overtemperature protection.
Low and adjustable OverCurrent Protection (OCP) trip level for both converters.
General purpose input for latched protection, e.g. to be used for system
OverTemperature Protection (OTP).
3. Applications
The device can be used in all applications that require an efficient and cost-effective
power supply solution up to 250 W. Notebook adapters in particular can benefit from
the high level of integration.
4. Ordering information
Table 1.
Ordering information
Package
Name
TEA1751T
TEA1751LT
SO16
SO16
Description
plastic small outline package; 16 leads; body width 3.9 mm
plastic small outline package; 16 leads; body width 3.9 mm
Version
SOT109-1
SOT109-1
Type number
TEA1751T_LT_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 23 December 2009
2 of 29
NXP Semiconductors
TEA1751T; TEA1751LT
GreenChip III SMPS control IC
5. Block diagram
PFCDRIVER
PFC DRIVER
1.12 V
3.5 V
FBDRIVER
13
FB DRIVER
DRV
80
μA
12
DRV
PFC GATE
5 LATCH
FB GATE
LOW
VIN
VINSENSE 7
BOOST
LATCH
RESET
LOW
POWER
1.25 V
EXT PROT
1.25 V
PROT
MAX
PFC PROT
PROT
ENABLE PFC
R
Q
S
Q
S
R
ENABLE
FB
Freq
Red.
LOW
POWER
PFC
OSC
VCC GOOD
VoSTART FB
LOW POWER
EXT PROT
PFC
PROT
TIMEOUT
EXT PROT
OTP
OvpFB
LATCH RESET
TIMEOUT
TON MAX
VoSHORT
V
UVLO
PROT
EXT PROT
V
startup
V
th(UVLO)
TON MAX
FB
OSC
Freq. Red.
SMPS
CONTROL
S (TEA1751L only)
S
LATCHED
S
PROTECTION
S
R
PROT
S (TEA1751 only)
S
SAFE
S RESTART
R PROTECTION
VCC GOOD
CHARGE
CONTROL
CHARGE
VALLEY
DETECT
INTERNAL
SUPPLY
V
startup
OvpFB
OPP
OPP
OVP
COUNTER
4 FBAUX
FB GATE
STARTFB
START STOP
PFC
OPP
MIN
OCP
TIME
OUT
2.5 V
3.5 V
PFCCOMP 6
30
μA
VOSENSE 9
2.50 V
2.7 V
15
μA
3.7 V
3 FBCTRL
BOOST
VoOVP
LOW VIN
VoSTART FB
VoSHORT
FB
DRIVER
BLANK
10 FBSENSE
OCP
BLANK
PFC DRIVER
ENABLE PFC
60
μA
PFCSENSE 11
500 mV
ENABLE FB
START FB
START
SOFT
60
μA
SOFT START
START STOP PFC
PFCAUX 8
VALLEY
DETECT
TIMER 4
μs
OTP
PFCGATE
ZCS
CHARGE
TIMER 50
μs
V
th(UVLO)
100 mV
ZCS
TEMP
OTP
80 mV
16
HV
1
V
CC
2
GND
014aaa299
Remark:
For the TEA1751L the time-out is latched.
For the TEA1751 the time-out is safe restart.
Fig 1.
Block diagram
TEA1751T_LT_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 23 December 2009
3 of 29
NXP Semiconductors
TEA1751T; TEA1751LT
GreenChip III SMPS control IC
6. Pinning information
6.1 Pinning
V
CC
GND
FBCTRL
FBAUX
LATCH
PFCCOMP
VINSENSE
PFCAUX
1
2
3
4
16 HV
15 HVS
14 HVS
13 FBDRIVER
TEA1751(L)T
5
6
7
8
014aaa300
12 PFCDRIVER
11 PFCSENSE
10 FBSENSE
9
VOSENSE
Fig 2.
Pin configuration: TEA1751(L)T (SOT109-1)
6.2 Pin description
Table 2.
Symbol
V
CC
GND
FBCTRL
FBAUX
LATCH
PFCCOMP
VINSENSE
PFCAUX
VOSENSE
FBSENSE
PFCSENSE
PFCDRIVER
FBDRIVER
HVS
HV
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14, 15
16
Description
supply voltage
ground
control input for flyback
input from auxiliary winding for demagnetization timing and
overvoltage protection for flyback
general purpose protection input
frequency compensation pin for PFC
sense input for mains voltage
input from auxiliary winding for demagnetization timing for PFC
sense input for PFC output voltage
programmable current sense input for flyback
programmable current sense input for PFC
gate driver output for PFC
gate driver output for flyback
high voltage safety spacer, not connected
high voltage start-up and valley sensing of flyback part
TEA1751T_LT_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 23 December 2009
4 of 29
NXP Semiconductors
TEA1751T; TEA1751LT
GreenChip III SMPS control IC
7. Functional description
7.1 General control
The TEA1751(L)T contains a controller for a power factor correction circuit as well as a
controller for a flyback circuit. A typical configuration is shown in
Figure 3.
12
8
6
11
9
16 13
10
TEA1751(L)T
7
3
2
4
1
014aaa301
Fig 3.
Typical configuration
7.1.1 Start-up and UnderVoltage LockOut (UVLO)
Initially the capacitor on the V
CC
pin is charged from the high voltage mains via the HV pin.
As long as V
CC
is below V
trip
, the charge current is low. This protects the IC if the V
CC
pin
is shorted to ground. For a short start-up time the charge current above V
trip
is increased
until V
CC
reaches V
th(UVLO)
. If V
CC
is between V
th(UVLO)
and V
startup
, the charge current is
low again, ensuring a low duty cycle during fault conditions.
The control logic activates the internal circuitry and switches off the HV charge current
when the voltage on pin V
CC
passes the V
startup
level. First, the LATCH pin current source
is activated and the soft start capacitors on the PFCSENSE and FBSENSE pins are
charged. When the LATCH pin voltage exceeds the V
en(LATCH)
voltage and the soft start
capacitor on the PFCSENSE pin is charged, the PFC circuit is activated. Also the flyback
converter is activated (providing the soft start capacitor on the FBSENSE pin is charged).
The output voltage of the flyback converter is then regulated to its nominal output voltage.
The IC supply is taken over by the auxiliary winding of the flyback converter. See
Figure 4.
If during start-up the LATCH pin does not reach the V
en(LATCH)
level before V
CC
reaches
V
th(UVLO)
, the LATCH pin output is deactivated and the charge current is switched on
again.
TEA1751T_LT_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 23 December 2009
5 of 29
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