DEVELOPMENT KIT
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4.8Designed for Short-Range Wireless Data Communications
Supports RF Data Transmission Rates Up to 115.2 kbps
3 V, Low Current Operation plus Sleep Mode
Up to 10 mW Transmitter Power
DR8000
916.50 MHz
Transceiver
Module
The DR8000 hybrid transceiver module is ideal for short-range wireless data applications where robust
operation, small size, low power consumption and low cost are required. The DR8000 utilizes RFM’s TR8000
amplifier-sequenced hybrid (ASH) architecture to achieve this unique blend of characteristics. All critical RF
functions are contained in the hybrid, simplifying and speeding design-in. The receiver section of the DR8000
is sensitive and stable. A wide dynamic range log detector, in combination with digital AGC and a compound
data slicer, provide robust performance in the presence of on-channel interference or noise. Two stages of
SAW filtering provide excellent receiver out-of-band rejection. The transmitter includes provisions for both on-
off keyed (OOK) and amplitude-shift keyed (ASK) modulation. The transmitter employs SAW filtering to
suppress output harmonics, facilitating compliance with FCC and similar regulations.
Absolute Maximum Ratings
Rating
Power Supply and All Input/Output Pins
Non-Operating Case Temperature
Soldering Temperature (10 seconds, 5 cycles maximum)
Value
-0.3 to +4.0
-50 to +100
260
Units
V
°C
°C
Electrical Characteristics
Characteristic
Operating Frequency
Data Modulation Type
OOK Data Rate
ASK Data Rate
Receiver Performance (OOK @ 4.8kbps)
Sensitivity, 4.8 kbps, 10-3 BER, AM Test Method
Input Current, 4.8 kbps, 3.0V Supply
Sensitivity, 19.2 kbps, 10-3 BER, AM Test Method
Input Current, 19.2 kbps, 3.0V Supply
Transmitter Performance (OOK @ 4.8kbps)
Peak RF Output Power, 315 µA TXMOD Current
Peak Current, 315 µA TXMOD Current
OOK Turn On/Turn Off Times
ASK Output Rise/Fall Times
Power Supply Voltage Range (including I/O)
Operating Ambient Temperature
Power Supply Voltage Ripple
Sym
f
o
Notes
Minimum
916.30
Typical
Maximum
916.70
Units
MHz
OOK/ASK
30
115.2
kb/s
kb/s
-108
4.2
-104
4.25
dBm
mA
dBm
mA
P
OL
I
TPL
t
ON
/t
OFF
t
TR
/t
TF
Vcc
T
A
2.2
-40
10
32
12/6
1.1/1.1
3.7
+85
10
dBm
mA
µs
µs
Vdc
°C
mVp-p
www.RFM.com
E-mail: info@rfm.com
©2008 by RF Monolithics, Inc.
Page 1 of 7
DR8000 - 4/8/08
DR8000 Pinout and Dimensions
1000 mils
900 mils
GND- 1
PKDET- 2
RX BBO- 3
GND- 4
RX- 5
TX- 6
LPFILT- 7
TX/RX- 8
OOK/ASK- 9
SLEEP- 10
20- GND
19- VCC
18- CFG CLK
17- CFG
DATA
16- RX CLK
15- 2G/3G
MODE
14- 4.8Kbps/19.2Kbps
13- GND
SC/DSSS
12- GND
MODE
11- GND
1000 mils
www.RFM.com
E-mail: info@rfm.com
©2008 by RF Monolithics, Inc.
Page 2 of 7
DR8000 - 4/8/08
Pin Descriptions
Pin
1,4,20
19
Name
GND
VCC
In/Out
-
-
GND is the ground pin.
VCC is a positive supply voltage pin.
Description
This pin is the peak detector output. A 0.022uF capacitor to ground (C5) sets the peak detector attack and
decay times, which have a fixed 1:1000 ratio. For most applications, these time constants should be coordi-
nated with the base-band time constant. For a given base-band capacitor C
BBO
, the capacitor value C
PKD
is:
C
PKD
= 2.0* C
BBO
, where C
BBO
and C
PKD
are in pF
2
PKDET
Out
A ±10% ceramic capacitor should be used at this pin. This time constant will vary between t
PKA
and 1.5* t
PKA
with variations in supply voltage, temperature, etc. The capacitor is driven from a 200 ohm “attack” source,
and decays through a 200 K load. The peak detector is used to drive the “dB-below-peak” data slicer and the
AGC release function. The peak detector capacitor is discharged in the receiver power-down (sleep) mode
and in the transmit modes. See the description of Pin 3 below for further information.
A 0.022uF capacitor is
installed for operation at 4.8kbps.
This pin is connected directly to the transceiver BBOUT pin. This pin drives the CMPIN pin through a coupling
capacitor, C
BBO
= 0.01uF (C4), for internal data slicer operation at 4.8kbps.
C
BBO
= 11.2*SP
MAX
, where SP
MAX
is the maximum signal pulse width in µs and C
BBO
is in pF
The nominal output impedance of this pin is 1 K.The BBOUT signal changes about 10 mV/dB, with a peak-to-
peak signal level of up to 450 mV. The signal at BBOUT is riding on a 1.5 Vdc value that varies somewhat
with supply voltage and temperature, so it should be coupled through a capacitor to an external load. When
an external data recovery process is used with AGC, BBOUT must be coupled to the external data recovery
process and CMPIN by separate series coupling capacitors. The output impedance of this pin becomes very
high in sleep mode, preserving the charge on the coupling capacitor.
The value of C3 on the circuit board has been chosen to match typical data encoding schemes at 4.8 kbps. If
C4 is modified to support higher data rates and/or different data encoding schemes and PK DET is being
used, make the value of the peak detector capacitor C5 about 2x the value of C
BBO
.
RXDATA is the receiver data output pin. It is a CMOS output. The signal on this pin can come from one of two
sources. The default source is directly from the output of the data slicer circuit. The alternate source is from
the radio’s internal data and clock recovery circuit. When the internal data and clock recovery circuit is used,
the signal on RXDATA is switched from the output of the data slicer to the output of the data and clock recov-
ery circuit when a packet start symbol is detected. Each recovered data bit is then output on the rising edge of
a RXDCLK pulse (Pin 16), and is stable for reading on the falling edge of the RXDCLK pulse.
The transmitter RF output voltage is proportional to the input current to this pin. A resistor in series with the
TXMOD input is normally used to adjust the peak transmitter output. Full transmitter power (10 mW) requires
about 315 µA of drive current. The transmitter output power P
O
for a 3 Vdc supply voltage is approximately:
PO = 101*(I
TXM
)
2
, where PO is in mW and the modulation current I
TXM
is in mA
6
TXMOD
In
The practical power control range is 10 to -50 dBm. A ±5% TXMOD resistor value is recommended. Internally,
this pin is connected to the base of a bipolar transistor with a small emitter resistor. The voltage at the
TXMOD input pin is about 0.87 volt with 315 uA of drive current. This pin accepts analog modulation and can
be driven with either logic level data pulses (unshaped) or shaped data pulses.
A series 6.2 kilohm resistor is installed to provide +10dBm average output power with a +3Vdc input.
This pin is the receiver low-pass filter bandwidth adjust. The filter bandwidth is set by a resistor R
LPF
(R4)
between this pin and ground. The resistor value can range from 510 K to 3 K, providing a filter 3 dB bandwidth
f
LPF
from 5 to 600 kHz. The resistor value is determined by:
7
LPFADJ
In
R
LPF
= (0.0006*f
LPF
)
-1.069
where R
LPF
is in kilohms, and f
LPF
is in kHz
A ±5% resistor should be used to set the filter bandwidth. This will provide a 3 dB filter bandwidth between
f
LPF
and 1.3* f
LPF
with variations in supply voltage, temperature, etc. The filter provides a three-pole, 0.05
degree equiripple phase response.
A 470 kilohm resistor to GND is installed to provide a 3dB filter band-
width of 5.275kHz. Connect an external ±1%, 243kilohm resistor to GND for 19.2kbps operation.
8
TX/RX
In
Logic Input (CMOS compatible). This pin, in 3G mode, selects the operation of the TR8000 . Pull this pin
‘High’ for Transmit Mode. Pull this pin ‘Low’ for Receive mode.
Do not allow this pin to float.
Logic Input (CMOS compatible). This pin, in 3G mode, selects the operation of the TR8000. Pull this pin
‘High’ for OOK Transmit/Receive mode. Pull this pin ‘Low’ for ASK Transmit/Receive mode.
Do not allow this
pin to float.
3
BBOUT
Out
5
RXDATA
Out
9
OOK/ASK
In
www.RFM.com
E-mail: info@rfm.com
©2008 by RF Monolithics, Inc.
Page 3 of 7
DR8000 - 4/8/08
Pin
10
Name
SLEEP
In/Out
In
Description
Logic Input (CMOS compatible). This pin, in 3G mode, puts the TR8000 into Sleep mode. Pull this pin ‘High’
for Sleep Mode. Pull this pin ‘Low’ for operation mode.
Do not allow this pin to float.
Logic Input (CMOS compatible). This pin, in 3G mode, enables the Start Vector Recognition circuit. The
TR8000 will not output a recovered clock on RXDCLK (pin 16) until the start vector, 0xE2E2, has been recog-
nized. Pull this pin ‘High’ to enable Start Vector Recognition. Pull this pin ‘Low’ then ‘High’ to reset the Start
Vector Recognition circuit.
Do not allow this pin to float.
Keep this pin pulled ‘Low’.
Keep this pin pulled ‘Low’.
11
SVEN
In
12
13
Not Used
Not Used
14
4.8KBPS/
19.2KBPS
In
Logic Input (CMOS compatible). This pin, in 3G mode, selects the receive data rate of the DR8000. Pull this
pin ‘High’ to select 4.8kbps. Pull this pin ‘Low’ to select 19.2kbps.
Do not allow this pin to float.
NOTE: Operating at 19.2kbps will require the value of C4, C5 and R4 to change to accommodate the
higher data rate. See the TR8000 datasheet for recommended component values.
Logic Input (CMOS compatible). This pin sets the processor to operate in 3G mode. The power-up operating
configuration of the TR8000 device is controlled by the J2 jumper setting. When DC power is applied to the
DR8000 with J2 installed across 2-3, this pin should be pulled ‘High’ immediately after power-up to initiate 3G
mode. Failure to pull pin 15 ‘High’ after power-up will cause the processor to remain inactive. Pulling this pin
‘High’ wakes the processor for 3G mode operation. When DC power is applied to the DR8000 with J2 installed
across 1-2, this pin should be held ‘Low’ to operate in 2G mode.
Do not allow this pin to float.
RXDCLK is the clock output from the data and clock recovery circuit. RXDCLK is a CMOS output. When the
radio’s internal data and clock recovery circuit is not used, RXDCLK is a steady low value. When the internal
data and clock recovery is used, RXDCLK is low until a packet start symbol is detected at the output of the
data slicer. Each bit following the start symbol is output at RXDATA on the rising edge of a RXDCLK pulse,
and is stable for reading on the falling edge of the RXDCLK pulse. Once RXDCLK is activated by the detec-
tion of a start symbol, it remains active until SVEN (pin 11) is reset. See Pin 11 description.
In 3G control mode, CFGDAT is a bi-directional CMOS logic pin. When CFG (Pin 19) is set to a logic 1, con-
figuration data can be clocked into or out of the radio’s configuration registers through CFGDAT using CFG-
CLK (Pin 18). Data clocked into CFGDAT is transferred to a control register each time a group of 8 bits is
received. Pulses on CFGCLK are used to clock configuration data into and out of the radio through CFGDAT.
When writing through CFGDAT, a data bit is clocked into the radio on the rising edge of a CFGCLK pulse.
When reading through CFGDAT, data is output on the rising edge of the CFGCLK pulse and is stable for
reading on the falling edge of the CFGCLK. Refer to the TR8000 datasheet for detailed timing. This pin is a
high impedance input (CMOS compatible) in 2G mode. This pin must be held at a logic level.
Do not allow
this pin to float.
In 3G control mode, pulses on CFGCLK are used to clock configuration data into and out of the radio through
CFGDAT (Pin 17). When writing to CFGDAT, a data bit is clocked into the radio on the rising edge of a CFG-
CLK pulse. When reading through CFGDAT, data is stable for reading on the falling edge of the CFGCLK.
Refer to the TR8000 datasheet for detailed timing. This pin is a high impedance input (CMOS compatible) in
2G mode.
Do not allow this pin to float.
15
3G SEL
In
16
RXDCLK
Out
17
CFGDAT
In/Out
18
CFGCLK
In/Out
www.RFM.com
E-mail: info@rfm.com
©2008 by RF Monolithics, Inc.
Page 4 of 7
DR8000 - 4/8/08
Theory of Operation
The DR8000 evaluation module is centered around the TR8000
ASH Transceiver. The DR8000 may operate in backward
compatible 2G mode, or in the enhanced 3G mode. Since 3G mode
requires the use of a serial I/O port to configure internal registers,
the module includes an on-board Silicon Labs C8051F330
microcontroller to control access to the serial port. When 2G mode
is enabled the microcontroller serves no function. When 3G mode
is enabled the microcontroller constantly scans pins 8-15 for a
change of logic state. When a state change is detected on one or
more of these pins, the microcontroller automatically updates the
internal configuration registers via the serial port of the TR8000.
The microcontroller assumes full control of the CFG pin, CFGCLK
pin, and CFGDAT pin in 3G mode to continuously update the
internal registers.
The DR8000 module is designed to demonstrate the performance
of the TR8000 ASH Transceiver at 4.8kbps, although other data
rates are possible with changes in on-board component values.
See pin descriptions and refer to the TR8000 datasheet.
The DR8000 module may be mounted on a prototype assembly
using standard 0.1” spacing, 10-pin headers spaced 0.9” apart.
2G Mode Operation
The DR8000 may operate in 2G mode. See pin 15 description and
Power-up Mode Select (J2) section for mode select details. In 2G
mode, the CFGCLK pin (18) and CFGDAT pin (17) operate as
CTRL0 and CTRL1, respectively, just as for second-generation
devices. The CFGCLK and CFGDAT pins are a high impedance
input allowing external control for 2G configuration. The logic levels
on CFGCLK (CTRL0) and CFGDAT (CTRL1) control the default 2G
operation as shown below:
CFGCLK (CNTRL0)
0
1
0
1
Current Consumption Monitor (J5)
The current consumption of the TR8000 device may be monitored
by removing J5 and connecting an ammeter across the terminals.
When J5 is removed it isolates the TR8000 from VCC powering the
on-board processor to give a true reading of the current
consumption of only the TR8000 without the additional current
usage of the processor. J5 must be installed to power the TR8000
if not using the header for current measurement.
Power-up Mode Select (J2)
J2 is used to select the operating mode of the TR8000 device
only
at power-up. The state of J2 when VCC is applied will determine
whether the board operates in 2G mode or 3G mode. Pin 2 (center
pin) of J2 is connected to Pin 19 (CFG) of the TR8000 device and
is grounded for 2G mode and functions as the chip select line for the
serial interface in 3G mode. Installing the jumper will either connect
the CFG pin of the TR8000 to GND or directly to the processor for
control in 3G mode. See the table below for power-up jumper
settings.
Setting
J2(1-2)
J2(2-3)
Power-up Mode
2G
3G
Pin 19
Connected to GND
Connected to Processor
After power-up if 3G mode is selected, pin 15 (3G Sel) must be
pulled ‘High’ to initiate the processor to operate in 3G mode. Failure
to pull pin 15 ‘High’ after power-up will cause the processor to
remain inactive.
CFGDAT (CNTRL1)
0
0
1
1
MODE
SLEEP
TX OOK
TX ASK
RX
J4
J5 Header
J2 Header
Programming Header (J4)
The programming header allows for custom firmware development
for the Silicon Labs C8051F330 if desired. Contact RFM for more
information about custom firmware development.
www.RFM.com
E-mail: info@rfm.com
©2008 by RF Monolithics, Inc.
Page 5 of 7
DR8000 - 4/8/08
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