ZL50232
32 Channel Voice Echo Canceller
Data Sheet
Features
•
Independent multiple channels of echo
cancellation; from 32 channels of 64 ms to 16
channels of 128 ms with the ability to mix
channels at 128 ms or 64 ms in any combination
Independent Power Down mode for each group
of 2 channels for power management
Fully compliant to ITU-T G.165, G.168 (2000) and
(2002) specifications
Passed all AT&T voice quality tests for carrier
grade echo canceller.
Compatible to ST-BUS and GCI interface at
2 Mbps serial PCM
PCM coding,
µ/A-Law
ITU-T G.711 or sign
magnitude
Per channel Fax/Modem G.164 2100Hz or G.165
2100Hz phase reversal Tone Disable
Per channel echo canceller parameters control
Transparent data transfer and mute
Fast reconvergence on echo path changes
Fully programmable convergence speeds
Patented Advanced Non-Linear Processor with
high quality subjective performance
Protection against narrow band signal
divergence and instability in high echo
environments
Ordering Information
ZL50232/QCC
ZL50232/GDC
ZL50232QCC1
100 Pin LQFP
208 Ball LBGA
100 Pin LQFP*
Trays
Trays
Trays
November 2004
•
•
•
•
•
•
•
•
•
•
•
•
* Pb Free Matte Tin
-
40°C to +85°C
•
•
•
•
•
+9 dB to -12 dB level adjusters (3 dB steps) at all
signal ports
Offset nulling of all PCM channels
10 MHz or 20 MHz master clock operation
3.3 V pads and 1.8 V Logic core operation with
5 V tolerant inputs
IEEE-1149.1 (JTAG) Test Access Port
Applications
•
•
•
•
•
•
Voice over IP network gateways
Voice over ATM, Frame Relay
T1/E1/J1 multichannel echo cancellation
Wireless base stations
Echo Canceller pools
DCME, satellite and multiplexer system
V
DD1 (3.3V)
V
SS
V
DD2 (1.8 V)
ODE
Echo Canceller Pool
Rin
Sin
MCLK
Fsel
PLL
Serial
to
Parallel
Group 0
ECA/ECB
Group 1
ECA/ECB
Group 2
ECA/ECB
Group 3
ECA/ECB
Parallel
to
Serial
Rout
Sout
Group 4
ECA/ECB
Group 5
ECA/ECB
Group 6
ECA/ECB
Group 7
ECA/ECB
Group 8
ECA/ECB
Group 9
ECA/ECB
Group 10
ECA/ECB
Group 11
ECA/ECB
Group 12
ECA/ECB
C4i
F0i
Timing
Unit
Group 13
ECA/ECB
Group 14
ECA/ECB
Group 15
ECA/ECB
Note:
Refer to Figure 4
for Echo Canceller
block diagram
IC0
RESET
Microprocessor Interface
Test Port
DS CS R/W A10-A0 DTA
D7-D0
IRQ TMS TDI TDO TCK TRST
Figure 1 - ZL50232 Device Overview
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved.
ZL50232
Description
Data Sheet
The ZL50232 Voice Echo Canceller implements a cost effective solution for telephony voice-band echo cancellation
conforming to ITU-T G.168 requirements. The ZL50232 architecture contains 16 groups of two echo cancellers
(ECA and ECB) which can be configured to provide two channels of 64 milliseconds or one channel of 128
milliseconds echo cancellation. This provides 32 channels of 64 milliseconds to 16 channels of 128 milliseconds
echo cancellation or any combination of the two configurations. The ZL50232 supports ITU-T G.165 and G.164 tone
disable requirements
PLLVSS1
PLLVSS2
PLLVDD
VDD1
VDD2
Mclk
NC
IC0
IC0
IC0
IC0
IC0
VDD1
77
VSS
fsel
NC
NC
NC
NC
NC
VSS
NC
NC
NC
78
TMS
TDI
TDO
TCK
VSS
TRSTB
IC0
RESETB
IRQB
DS
CS
R/W
DTA
NC
76
100
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
99
98
97
96
95
94
93
(100 pin LQFP)
92
ZL50232QC
91
90
89
88
87
86
85
84
83
82
81
80
79
NC
NC
NC
IC0
IC0
IC0
VSS
IC0
IC0
IC0
IC0
VDD2
C4ib
Foib
Rin
Sin
Rout
Sout
ODE
VSS
NC
NC
NC
NC
NC
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
VDD2
D0
D1
D2
VSS
D3
D4
D5
D6
D7
NC
NC
V
DD1
= 3.3 V
V
DD2
= 1.8 V
51
30
31
50
VSS
IC0
VSS
NC
VDD1
VDD2
A10
NC
VDD1
IC0
NC
NC
NC
A6
Figure 2 - 100 Pin LQFP
2
Zarlink Semiconductor Inc.
NC
NC
A0
A1
A2
A3
A4
A5
A7
A8
A9
26
27
28
29
32
33
34
35
36
37
38
39
41
40
42
43
45
44
46
47
48
49
ZL50232
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Data Sheet
16
A
V
SS
IC0
IC0
V
SS
IC0
c4i
V
DD1
V
DD1
IC0
V
SS
Rin
Sout
V
DD1
Rout
IC0
V
SS
Sin
IC0
V
SS
ODE
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
B
V
SS
IC0
F0i
V
SS
V
SS
V
DD2
V
SS
V
DD1
V
DD1
V
DD1
V
SS
V
SS
C
IC0
V
SS
V
DD1
V
SS
V
SS
V
SS
V
SS
NC
D
NC
IC0
V
DD1
V
SS
V
DD1
V
DD2
V
DD1
V
SS
V
DD1
V
SS
V
DD1
V
SS
V
SS
V
DD1
NC
IC0
A10
E
NC
IC0
V
SS
V
SS
V
DD1
V
SS
V
DD1
A9
F
NC
NC
V
DD1
V
DD1
V
SS
ZL50232GD
V
SS
V
SS
V
SS
V
SS
IC0
A8
G
NC
MCLK
V
SS
V
DD1
V
SS
V
DD1
V
DD2
V
DD2
NC
A7
H
NC
Fsel
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A6
J
NC
IC0
V
DD2
V
DD2
V
DD1
V
DD1
NC
A5
K
NC
IC0 PLLVSS PLLVDD
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A4
L
NC
NC
V
SS
V
DD1
V
SS
V
SS
V
SS
V
DD1
V
SS
V
DD1
V
SS
V
SS
R/W
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
SS
V
SS
V
SS
DS
V
DD2
V
DD2
V
DD1
V
DD1
V
DD1
V
DD1
NC
A3
M
TDI
TMS
V
SS
V
SS
V
SS
DTA
V
SS
V
SS
V
SS
IRQ
V
SS
V
SS
CS
V
SS
V
DD1
V
SS
V
SS
V
SS
V
SS
V
DD1
V
DD1
V
SS
A2
TDO
N
TCK
P
R
IC0
TRST
V
SS
V
SS
A1
V
DD1
V
DD1
A0
RESET
VDD1
V
SS
V
SS
V
SS
T
V
SS
D0
D1
D2
D3
D4
D5
D6
D7
1
- A1 corner is identified by metallized markings.
Figure 3 - 208 Ball LBGA
3
Zarlink Semiconductor Inc.
ZL50232
Pin Description
Pin #
Pin
Name
208-Ball LBGA
V
SS
100 Pin
LQFP
Description
Data Sheet
A1, A3,A7,A11, A13,
5, 18, 32,
Ground.
A15, A16, B2, B6, B8,
42, 56, 69,
B12, B14, B15, B16, C3, 81, 98
C5, C7, C9, C11, C12,
C13, C14, C16, D4, D8,
D10, D12, D13, E3, E4,
E14, F13, G3, G4, G7,
G8, G9, G10, H7, H8,
H9, H10, H13, H14, J7,
J8, J9, J10, K7, K8, K9,
K10, K13, K14, L3, L4,
M13, M14, M15, N3, N4,
N5, N7, N9, N11, N13,
P2, P3, P5, P7, P9.P11,
P13, P14, R2, R14,
R15, R16, T1, T3, T7,
T10, T14, T16
27, 48, 77,
Positive Power Supply.
Nominally 3.3 V (I/O Voltage).
A5, A9, B10, C4, C8,
100
B4, C10, D3, D5, D7,
D9, D11, D14, E13, F3,
F4, F14, H3, H4, J13,
J14, L13, L14, M3, M4,
N6, N8, N10, N14, N15,
P4, P6, P8, P10, P15,
R4, R6, R8, R10, R12,
T5, T12
C6, D6, J3, J4, N12,
P12, G13, G14
14, 37, 64,
Positive Power Supply.
Nominally 1.8 V (Core Voltage).
91
V
DD1
V
DD2
IC0
E15, F15, A12, A10, A6, 7, 41, 43,
Internal Connection.
These pins must be connected to V
SS
for
A2, B1, B3, C1, C2, D2, 65, 66, 67, normal operation.
E2, J2, K2, R1
68, 70, 71,
72, 86, 87,
88, 93, 94
A14, C15, D1, D15, E1,
F1, G1, G15, H1, H15,
J1, J15, K1,
K15,L1,L15,F2,L2
24, 25, 26,
No connection.
These pins must be left open for normal
44, 45, 46, operation.
47, 49, 51,
52, 53, 54,
55, 73, 74,
75, 76, 78,
79, 80, 82,
83, 84, 85,
89, 99, 50
9
Interrupt Request (Open Drain Output).
This output goes low
when an interrupt occurs in any channel. IRQ returns high when
all the interrupts have been read from the Interrupt FIFO
Register. A pull-up resistor (1 K typical) is required at this output.
NC
IRQ
R9
4
Zarlink Semiconductor Inc.
ZL50232
Pin Description (continued)
Pin #
Pin
Name
208-Ball LBGA
DS
CS
R/W
DTA
R11
R13
R5
R7
100 Pin
LQFP
10
11
12
13
Description
Data Sheet
Data Strobe (Input).
This active low input works in conjunction
with CS to enable the read and write operations.
Chip Select (Input).
This active low input is used by a
microprocessor to activate the microprocessor port.
Read/Write (Input).
This input controls the direction of the data
bus lines (D7-D0) during a microprocessor access.
Data Transfer Acknowledgment (Open Drain Output).
This
active low output indicates that a data bus transfer is completed.
A pull-up resistor (1 K typical) is required at this output.
D0..D7
T2,T4,T6,T8,T9,T11,
T13,T15
15, 16, 17,
Data Bus D0 - D7 (Bidirectional).
These pins form the 8 bit
19, 20, 21, bidirectional data bus of the microprocessor port.
22, 23
A0..A10
P16,N16,M16,L16,K16, 28, 29, 30,
Address A0 to A10 (Input).
These inputs provide the A10 - A0
J16,H16,G16,F16,E16, 31, 33, 34, address lines to the internal registers.
D16
35, 36, 38,
39, 40
ODE
B13
57
Output Drive Enable (Input).
This input pin is logically AND’d
with the ODE bit-6 of the Main Control Register. When both ODE
bit and ODE input pin are high, the Rout and Sout ST-BUS
outputs are enabled.
When the ODE bit is low or the ODE input pin is low, the Rout
and Sout ST-BUS outputs are high impedance.
Send PCM Signal Output (Output).
Port 1 TDM data output
streams. Sout pin outputs serial TDM data streams at
2.048 Mbps with 32 channels per stream.
Receive PCM Signal Output (Output).
Port 2 TDM data output
streams. Rout pin outputs serial TDM data streams at
2.048 Mbps with 32 channels per stream.
Send PCM Signal Input (Input).
Port 2 TDM data input streams.
Sin pin receives serial TDM data streams at 2.048 Mbps with 32
channels per stream.
Receive PCM Signal Input (Input).
Port 1 TDM data input
streams. Rin pin receives serial TDM data streams at
2.048 Mbps with 32 channels per stream.
Frame Pulse (Input).
This input accepts and automatically
identifies frame synchronization signals formatted according to
ST-BUS or GCI interface specifications.
Serial Clock (Input).
4.096 MHz serial clock for shifting data
in/out on the serial streams (Rin, Sin, Rout, Sout).
Master Clock (Input).
Nominal 10 MHz or 20 MHz Master Clock
input. May be connected to an asynchronous (relative to frame
signal) clock source.
Sout
A8
58
Rout
B9
59
Sin
B11
60
Rin
B7
61
F0i
B5
62
C4i
MCLK
A4
G2
63
90
5
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