AT49LV1024A-45VC datasheet, PDF

Datasheet> All Categories > storage> storage> AT49LV1024A-45VC

AT49LV1024A-45VC: Description64K X 16 FLASH 3V PROM, 45 ns, PDSO40; Categorystorage storage; File Size125KB，14 Pages; ManufacturerAtmel (Microchip)

Download Datasheet Parametric Compare View All

AT49LV1024A-45VC Overview

64K X 16 FLASH 3V PROM, 45 ns, PDSO40

AT49LV1024A-45VC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Atmel (Microchip)
Parts packaging code	TSOP1
package instruction	TSSOP, TSSOP40,.56,20
Contacts	40
Reach Compliance Code	compli
ECCN code	EAR99
Maximum access time	45 ns
startup block	BOTTOM
command user interface	YES
Data polling	YES
JESD-30 code	R-PDSO-G40
JESD-609 code	e0
length	12.4 mm
memory density	1048576 bi
Memory IC Type	FLASH
memory width	16
Humidity sensitivity level	3
Number of functions	1
Number of departments/size	1,1
Number of terminals	40
word count	65536 words
character code	64000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	64KX16
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP40,.56,20
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	240
power supply	3.3 V
Programming voltage	3 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Department size	8K,56K
Maximum standby current	0.0005 A
Maximum slew rate	0.02 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
switch bit	YES
type	NOR TYPE
width	10 mm

Preview

Download Datasheet

View All

Features

•

Single-voltage Operation Read/Write Operation: 2.7V to 3.6V (BV). 3.0V to 3.6V(LV)

Fast Read Access Time – 45 ns

Internal Program Control and Timer

8K Word Boot Block with Lockout

Fast Erase Cycle Time – 1.5 Seconds

Word-by-word Programming – 20 µs/Word Typical

Hardware Data Protection

Data Polling for End of Program Detection

Small 10 x 14 mm VSOP Package

Typical 10,000 Write Cycles

Description

The AT49BV/LV1024A is a 3-volt only in-system Flash memory. The 1-megabit of

memory is organized as 65,536 words by 16 bits. Manufactured with Atmel’s

advanced nonvolatile CMOS technology, the devices offer access times to 45 ns with

power dissipation of just 72 mW over the industrial temperature range.

To allow for simple in-system reprogrammability, the AT49BV/LV1024A does not

require high input voltages for programming. Three-volt-only commands determine the

read and programming operation of the device. Reading data out of the device is simi-

lar to reading from an EPROM. Reprogramming the AT49BV/LV1024A is performed

by erasing a block of data (entire chip or main memory block) and then programming

on a word by word basis. The typical word programming time is a fast 20 µs. The end

of a program cycle can be optionally detected by the Data Polling feature. Once the

end of a word program cycle has been detected, a new access for a read or program

can begin. The typical number of program and erase cycles is in excess of 10,000

cycles.

The optional 8K word boot block section includes a reprogramming write lock out fea-

ture to provide data integrity. The boot sector is designed to contain user secure code,

and when the feature is enabled, the boot sector is permanently protected from being

erased or reprogrammed.

1-megabit

(64K x 16)

3-volt Only

Flash Memory

AT49BV1024A

AT49LV1024A

Pin Configurations

Pin Name

A0 - A15

I/O0 - I/O15

Function

Addresses

Chip Enable

Output Enable

Write Enable

Data Inputs/Outputs

No Connect

AT49BV/LV1024A VSOP Top View

Type 1

10 x 14 mm

A10

A11

A12

A13

A14

A15

VCC

I/O15

I/O14

I/O13

I/O12

I/O11

I/O10

I/O9

I/O8

GND

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

GND

Rev. 3332B–FLASH–12/03

Block Diagram

VCC

GND

DATA INPUTS/OUTPUTS

I/O15 - I/O0

OE, CE, AND WE

LOGIC

DATA LATCH

INPUT/OUTPUT

BUFFERS

Y-GATING

FFFFH

MAIN MEMORY

(56K WORDS)

OPTIONAL BOOT

BLOCK (8K WORDS)

2000H

1FFFH

0000H

Y DECODER

ADDRESS

INPUTS

X DECODER

Device Operation

READ:

The AT49BV/LV1024A is accessed like an EPROM. When CE and OE are low

and WE is high, the data stored at the memory location determined by the address pins

is asserted on the outputs. The outputs are put in the high-impedance state whenever

CE or OE is high. This dual-line control gives designers flexibility in preventing bus

contention.

CHIP ERASE:

When the boot block programming lockout feature is not enabled, the

boot block and the main memory block will erase together from the same Chip Erase

command (See Command Definitions table). If the boot block lockout function has been

enabled, data in the boot section will not be erased. However, data in the main memory

section will be erased. After a chip erase, the device will return to the read mode.

MAIN MEMORY ERASE:

As an alternative to the chip erase, a main memory block

erase can be performed, which will erase all words not located in the boot block region

to an FFFFH. Data located in the boot region will not be changed during a main memory

block erase. The Main Memory Erase command is a six-bus cycle operation. The

address (555H) is latched on the falling edge of the sixth cycle while the 30H data input

is latched on the rising edge of WE. The main memory erase starts after the rising edge

of WE of the sixth cycle. Please see Main Memory Erase cycle waveforms. The main

memory erase operation is internally controlled; it will automatically time to completion.

WORD PROGRAMMING:

Once the memory array is erased, the device is programmed

(to a logic “0”) on a word-by-word basis. Please note that a data “0” cannot be pro-

grammed back to a “1”; only erase operations can convert “0”s to “1”s. Programming is

accomplished via the internal device command register and is a four-bus cycle opera-

tion (please refer to the Command Definitions table). The device will automatically

generate the required internal program pulses.

The program cycle has addresses latched on the falling edge of WE or CE, whichever

occurs last, and the data latched on the rising edge of WE or CE, whichever occurs first.

Programming is completed after the specified t

cycle time. The Data Polling feature

may also be used to indicate the end of a program cycle.

BOOT BLOCK PROGRAMMING LOCKOUT:

The device has one designated block

that has a programming lockout feature. This feature prevents programming of data in

the designated block once the feature has been enabled. The size of the block is 8K

words. This block, referred to as the boot block, can contain secure code that is used to

bring up the system. Enabling the lockout feature will allow the boot code to stay in the

AT49BV/LV1024A

3332B–FLASH–12/03

AT49BV/LV1024A

device while data in the rest of the device is updated. This feature does not have to be

activated; the boot block’s usage as a write-protected region is optional to the user. The

address range of the boot block is 0000H to 1FFFH.

Once the feature is enabled, the data in the boot block can no longer be erased or pro-

grammed. Data in the main memory block can still be changed through the regular

programming method and can be erased using either the Chip Erase or the Main Mem-

ory Block Erase command. To activate the lockout feature, a series of six program

commands to specific addresses with specific data must be performed. Please refer to

the Command Definitions table.

BOOT BLOCK LOCKOUT DETECTION:

A software method is available to determine if

programming of the boot block section is locked out. When the device is in the software

product identification mode (see Software Product Identification Entry and Exit sections)

a read from address location 0002H will show if programming the boot block is locked

out. If the data on I/O0 is low, the boot block can be programmed; if the data on I/O0 is

high, the program lockout feature has been activated and the block cannot be pro-

grammed. The software product identification exit code should be used to return to

standard operation.

PRODUCT IDENTIFICATION:

The product identification mode identifies the device and

manufacturer as Atmel. It may be accessed by hardware or software operation. The

hardware operation mode can be used by an external programmer to identify the correct

programming algorithm for the Atmel product.

For details, see “Operating Modes” (for hardware operation) or “Software Product Identi-

fication Entry/Exit” on page 11. The manufacturer and device code is the same for both

modes.

DATA POLLING:

The AT49BV/LV1024A features Data Polling to indicate the end of a

program or erase cycle. During a program cycle an attempted read of the last byte

loaded will result in the complement of the loaded data on I/O7. Once the program cycle

has been completed, true data is valid on all outputs and the next cycle may begin. Data

Polling may begin at any time during the program cycle.

TOGGLE BIT:

In addition to Data Polling, the AT49BV/LV1024A provides another

method for determining the end of a program or erase cycle. During a program or erase

operation, successive attempts to read data from the device will result in I/O6 toggling

between one and zero. Once the program cycle has completed, I/O6 will stop toggling

and valid data will be read. Examining the toggle bit may begin at any time during a pro-

gram cycle.

HARDWARE DATA PROTECTION:

Hardware features protect against inadvertent

writes to the AT49BV/LV1024A in the following ways: (a) V

sense: if V

is below

1.8V (typical), the program function is inhibited. (b) Program inhibit: holding any one of

OE low, CE high or WE high inhibits program cycles. (c) Noise filter: pulses of less than

15 ns (typical) on the WE or CE inputs will not initiate a program cycle.

3332B–FLASH–12/03

AT49LV1024A-45VC Related Products

	AT49LV1024A-45VC	AT49BV1024A	AT49LV1024A
Description	64K X 16 FLASH 3V PROM, 45 ns, PDSO40	64K X 16 FLASH 3V PROM, 45 ns, PDSO40	64K X 16 FLASH 3V PROM, 45 ns, PDSO40
memory width	16	16	16
Number of functions	1	1	1
Number of terminals	40	40	40
Maximum operating temperature	70 °C	70 Cel	70 Cel
Minimum operating temperature	-	0.0 Cel	0.0 Cel
organize	64KX16	64K X 16	64K X 16
surface mount	YES	Yes	Yes
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	GULL WING	GULL WING	GULL WING
Terminal location	DUAL	DUAL	DUAL
Maximum supply/operating voltage	-	3.6 V	3.6 V
Minimum supply/operating voltage	-	3 V	3 V
Rated supply voltage	-	3.3 V	3.3 V
maximum access time	-	45 ns	45 ns
Processing package description	-	10 X 14 MM, LEAD FREE, PLASTIC, MO-142CA, VSOP-40	10 X 14 MM, LEAD FREE, PLASTIC, MO-142CA, VSOP-40
Lead-free	-	Yes	Yes
EU RoHS regulations	-	Yes	Yes
state	-	DISCONTINUED	DISCONTINUED
Craftsmanship	-	CMOS	CMOS
packaging shape	-	RECTANGULAR	RECTANGULAR
Package Size	-	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Terminal spacing	-	0.5000 mm	0.5000 mm
terminal coating	-	MATTE TIN	MATTE TIN
Packaging Materials	-	PLASTIC/EPOXY	PLASTIC/EPOXY
storage density	-	1.05E6 deg	1.05E6 deg
operating mode	-	ASYNCHRONOUS	ASYNCHRONOUS
Number of digits	-	64K	64K
Memory IC type	-	FLASH 3V PROM	FLASH 3V PROM
serial parallel	-	PARALLEL	PARALLEL

Recommended Resources

Half-bridge power conversion circuit diagram

Voice-activated music lantern circuit (2)

Competition digital display device circuit

STK085-105 audio IC circuit diagram

LT1044 negative voltage generator circuit diagram

Computer motherboard circuit diagram 815 1_19

A few questions for beginners: I bought a moto linux phone and want to do some small development. I have no experience in linux development, only windows development. There are some questions I don't understand. I hope you can guid...; xoao Embedded System

compilation: If anyone has the MCU assembly data, I would like to thank you. [email]lv499970142@gmail.com[/email] My email address is...; lv499970142 TI Technology Forum

[Telink's new generation of low-power, high-performance, multi-protocol wireless kit B91 review] Run the Zigbee gateway: [i=s]This post was last edited by damiaa on 2022-9-12 18:07[/i][Telink's new generation of low-power, high-performance, multi-protocol wireless kit B91 review] Run the Zigbee gateway After running the...; damiaa Domestic Chip Exchange

51 single-chip microcomputer...: Can any expert tell me why I can't see the program I wrote when I burned it into my microcontroller? What's going on?...; wx8028 Embedded System

Dual Ultra-Low Dropout Regulator: Please recommend a dual-channel ultra-low dropout regulator similar to LP3986TL-3333. The input voltage is 3.3V, the output voltage is also 3.3V, and the output current is about 150mA. The main thing ...; luckyCY Power technology

wxf0204 is a good comrade, who cares for the collective and others: wxf0204 is a good comrade, who cares for the collective and others...; mdice1986 Embedded System

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

Popular Components