Features
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Single-voltage Operation Read/Write Operation: 2.7V to 3.6V (BV). 3.0V to 3.6V(LV)
Fast Read Access Time – 45 ns
Internal Program Control and Timer
8K Word Boot Block with Lockout
Fast Erase Cycle Time – 1.5 Seconds
Word-by-word Programming – 20 µs/Word Typical
Hardware Data Protection
Data Polling for End of Program Detection
Small 10 x 14 mm VSOP Package
Typical 10,000 Write Cycles
Description
The AT49BV/LV1024A is a 3-volt only in-system Flash memory. The 1-megabit of
memory is organized as 65,536 words by 16 bits. Manufactured with Atmel’s
advanced nonvolatile CMOS technology, the devices offer access times to 45 ns with
power dissipation of just 72 mW over the industrial temperature range.
To allow for simple in-system reprogrammability, the AT49BV/LV1024A does not
require high input voltages for programming. Three-volt-only commands determine the
read and programming operation of the device. Reading data out of the device is simi-
lar to reading from an EPROM. Reprogramming the AT49BV/LV1024A is performed
by erasing a block of data (entire chip or main memory block) and then programming
on a word by word basis. The typical word programming time is a fast 20 µs. The end
of a program cycle can be optionally detected by the Data Polling feature. Once the
end of a word program cycle has been detected, a new access for a read or program
can begin. The typical number of program and erase cycles is in excess of 10,000
cycles.
The optional 8K word boot block section includes a reprogramming write lock out fea-
ture to provide data integrity. The boot sector is designed to contain user secure code,
and when the feature is enabled, the boot sector is permanently protected from being
erased or reprogrammed.
1-megabit
(64K x 16)
3-volt Only
Flash Memory
AT49BV1024A
AT49LV1024A
Pin Configurations
Pin Name
A0 - A15
CE
OE
WE
I/O0 - I/O15
NC
Function
Addresses
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
No Connect
AT49BV/LV1024A VSOP Top View
Type 1
10 x 14 mm
A9
A10
A11
A12
A13
A14
A15
NC
WE
VCC
NC
CE
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
I/O8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
GND
A8
A7
A6
A5
A4
A3
A2
A1
A0
OE
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
GND
Rev. 3332B–FLASH–12/03
1
Block Diagram
VCC
GND
OE
WE
CE
DATA INPUTS/OUTPUTS
I/O15 - I/O0
16
OE, CE, AND WE
LOGIC
DATA LATCH
INPUT/OUTPUT
BUFFERS
Y-GATING
FFFFH
MAIN MEMORY
(56K WORDS)
OPTIONAL BOOT
BLOCK (8K WORDS)
2000H
1FFFH
0000H
Y DECODER
ADDRESS
INPUTS
X DECODER
Device Operation
READ:
The AT49BV/LV1024A is accessed like an EPROM. When CE and OE are low
and WE is high, the data stored at the memory location determined by the address pins
is asserted on the outputs. The outputs are put in the high-impedance state whenever
CE or OE is high. This dual-line control gives designers flexibility in preventing bus
contention.
CHIP ERASE:
When the boot block programming lockout feature is not enabled, the
boot block and the main memory block will erase together from the same Chip Erase
command (See Command Definitions table). If the boot block lockout function has been
enabled, data in the boot section will not be erased. However, data in the main memory
section will be erased. After a chip erase, the device will return to the read mode.
MAIN MEMORY ERASE:
As an alternative to the chip erase, a main memory block
erase can be performed, which will erase all words not located in the boot block region
to an FFFFH. Data located in the boot region will not be changed during a main memory
block erase. The Main Memory Erase command is a six-bus cycle operation. The
address (555H) is latched on the falling edge of the sixth cycle while the 30H data input
is latched on the rising edge of WE. The main memory erase starts after the rising edge
of WE of the sixth cycle. Please see Main Memory Erase cycle waveforms. The main
memory erase operation is internally controlled; it will automatically time to completion.
WORD PROGRAMMING:
Once the memory array is erased, the device is programmed
(to a logic “0”) on a word-by-word basis. Please note that a data “0” cannot be pro-
grammed back to a “1”; only erase operations can convert “0”s to “1”s. Programming is
accomplished via the internal device command register and is a four-bus cycle opera-
tion (please refer to the Command Definitions table). The device will automatically
generate the required internal program pulses.
The program cycle has addresses latched on the falling edge of WE or CE, whichever
occurs last, and the data latched on the rising edge of WE or CE, whichever occurs first.
Programming is completed after the specified t
BP
cycle time. The Data Polling feature
may also be used to indicate the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT:
The device has one designated block
that has a programming lockout feature. This feature prevents programming of data in
the designated block once the feature has been enabled. The size of the block is 8K
words. This block, referred to as the boot block, can contain secure code that is used to
bring up the system. Enabling the lockout feature will allow the boot code to stay in the
2
AT49BV/LV1024A
3332B–FLASH–12/03
AT49BV/LV1024A
device while data in the rest of the device is updated. This feature does not have to be
activated; the boot block’s usage as a write-protected region is optional to the user. The
address range of the boot block is 0000H to 1FFFH.
Once the feature is enabled, the data in the boot block can no longer be erased or pro-
grammed. Data in the main memory block can still be changed through the regular
programming method and can be erased using either the Chip Erase or the Main Mem-
ory Block Erase command. To activate the lockout feature, a series of six program
commands to specific addresses with specific data must be performed. Please refer to
the Command Definitions table.
BOOT BLOCK LOCKOUT DETECTION:
A software method is available to determine if
programming of the boot block section is locked out. When the device is in the software
product identification mode (see Software Product Identification Entry and Exit sections)
a read from address location 0002H will show if programming the boot block is locked
out. If the data on I/O0 is low, the boot block can be programmed; if the data on I/O0 is
high, the program lockout feature has been activated and the block cannot be pro-
grammed. The software product identification exit code should be used to return to
standard operation.
PRODUCT IDENTIFICATION:
The product identification mode identifies the device and
manufacturer as Atmel. It may be accessed by hardware or software operation. The
hardware operation mode can be used by an external programmer to identify the correct
programming algorithm for the Atmel product.
For details, see “Operating Modes” (for hardware operation) or “Software Product Identi-
fication Entry/Exit” on page 11. The manufacturer and device code is the same for both
modes.
DATA POLLING:
The AT49BV/LV1024A features Data Polling to indicate the end of a
program or erase cycle. During a program cycle an attempted read of the last byte
loaded will result in the complement of the loaded data on I/O7. Once the program cycle
has been completed, true data is valid on all outputs and the next cycle may begin. Data
Polling may begin at any time during the program cycle.
TOGGLE BIT:
In addition to Data Polling, the AT49BV/LV1024A provides another
method for determining the end of a program or erase cycle. During a program or erase
operation, successive attempts to read data from the device will result in I/O6 toggling
between one and zero. Once the program cycle has completed, I/O6 will stop toggling
and valid data will be read. Examining the toggle bit may begin at any time during a pro-
gram cycle.
HARDWARE DATA PROTECTION:
Hardware features protect against inadvertent
writes to the AT49BV/LV1024A in the following ways: (a) V
CC
sense: if V
CC
is below
1.8V (typical), the program function is inhibited. (b) Program inhibit: holding any one of
OE low, CE high or WE high inhibits program cycles. (c) Noise filter: pulses of less than
15 ns (typical) on the WE or CE inputs will not initiate a program cycle.
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3332B–FLASH–12/03
Command Definition (in Hex)
Command
Sequence
Read
Chip Erase
Main Memory Erase
Word Program
Boot Block Lockout
(3)
Product ID Entry
Product ID Exit
(4)
Bus
Cycles
1
6
6
4
6
3
3
1st Bus
Cycle
Addr
Addr
555
555
555
555
555
555
Data
D
OUT
AA
AA
AA
AA
AA
AA
AAA
(2)
AAA
AAA
AAA
AAA
AAA
55
55
55
55
55
55
555
555
555
555
555
555
80
80
A0
80
90
F0
555
555
Addr
555
AA
AA
D
IN
AA
AAA
55
555
40
AAA
AAA
55
55
555
555
10
30
2nd Bus
Cycle
Addr
Data
3rd Bus
Cycle
Addr
Data
4th Bus
Cycle
Addr
Data
5th Bus
Cycle
Addr
Data
6th Bus
Cycle
Addr
Data
Product ID Exit
(4)
1
xxx
F0
Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex).
The ADDRESS FORMAT in each bus cycle is as follows: A11 - A0 (Hex); A11 - A15 (Don’t Care).
2. Since A11 is a Don’t Care, AAA can be replaced with 2AA.
3. The 8K word boot sector has the address range 0000H to 1FFFH.
4. Either one of the Product ID Exit commands can be used.
Absolute Maximum Ratings*
Temperature under Bias ................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to V
CC
+ 0.6V
Voltage on OE
with Respect to Ground ...................................-0.6V to +13.5V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
4
AT49BV/LV1024A
3332B–FLASH–12/03
AT49BV/LV1024A
DC and AC Operating Range
AT49LV1024A-45
Operating
Temperature (Case)
V
CC
Power Supply
Ind.
-40° C - 85° C
3.0V to 3.6V
Operating Modes
Mode
Read
Program
(2)
Standby/Write Inhibit
Program Inhibit
Program Inhibit
Output Disable
Product Identification
Hardware
V
IL
V
IL
V
IH
A1 - A15 = V
IL
, A9 = V
H(3)
, A0 = V
IL
A1 - A15 = V
IL
, A9 = V
H(3)
, A0 = V
IH
A0 = V
IL
, A1 - A15 = V
IL
A0 = V
IH
, A1 - A15 = V
IL
Notes:
1.
2.
3.
4.
5.
X can be V
IL
or V
IH
.
Refer to AC Programming Waveforms.
V
H
= 12.0V ± 0.5V.
Manufacturer Code: 001FH; Device Code: 0087H.
See details under “Software Product Identification Entry/Exit” on page 11.
Manufacturer Code
(4)
Device Code
(4)
Manufacturer Code
(4)
Device Code
(4)
CE
V
IL
V
IL
V
IH
X
X
X
OE
V
IL
V
IH
X
(1)
X
V
IL
V
IH
WE
V
IH
V
IL
X
V
IH
X
X
High-Z
Ai
Ai
Ai
X
I/O
D
OUT
D
IN
High-Z
Software
(5)
DC Characteristics
Symbol
I
LI
I
LO
I
SB1
I
SB2
I
CC(1)
V
IL
V
IH
V
OL
V
OH1
Note:
Parameter
Input Load Current
Output Leakage Current
V
CC
Standby Current CMOS
V
CC
Standby Current TTL
V
CC
Active Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
1. In the erase mode, I
CC
is 40 mA.
I
OL
= 2.1 mA
I
OH
= -400 µA
2.4
2.0
0.45
Condition
V
IN
= 0V to V
CC
V
I/O
= 0V to V
CC
CE = V
CC
- 0.3V to V
CC
CE = 2.0V to V
CC
f = 5 MHz; I
OUT
= 0 mA
Min
Max
10.0
10.0
50.0
0.5
20.0
0.6
Units
µA
µA
µA
mA
mA
V
V
V
V
5
3332B–FLASH–12/03
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