Features
•
32-Mbit Flash and 4-Mbit/8-Mbit SRAM
•
Single 66-ball (8 mm x 10 mm x 1.2 mm) CBGA Package
•
2.7V to 3.3V Operating Voltage
Flash
•
2.7V to 3.3V Read/Write
•
Access Time – 70 ns
•
Sector Erase Architecture
•
•
•
– Sixty-three 32K WordSectors with Individual Write Lockout
– Eight 4K Word Sectors with Individual Write Lockout
Fast Word Program Time – 15 µs
Sector Erase Time – 300 ms
Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming from Any Sector by Suspending Erase of a
Different Sector
– Supports Reading Any Word by Suspending Programming of Any Other Word
Low-power Operation
– 12 mA Active
– 13 µA Standby
Data Polling, Toggle Bit, Ready/Busy for End of Program Detection
VPP Pin for Write Protection and Accelerated Program/Erase Operations
RESET Input for Device Initialization
Sector Lockdown Support
Top or Bottom Boot Block Configuration Available
128-bit Protection Register
Minimum 100,000 Erase Cycles
•
•
•
•
•
•
•
•
32-megabit
Flash
+ 4-megabit/
8-megabit
SRAM
Stack Memory
AT52BR3224A
AT52BR3224AT
AT52BR3228A
AT52BR3228AT
SRAM
•
•
•
•
•
•
4-megabit (256K x 16)/8-megabit (512K x 16)
2.7V to 3.3V V
CC
70 ns Access Time
Fully Static Operation and Tri-state Output
1.2V (Min) Data Retention
Industrial Temperature Range
Device Number
AT52BR3224A
AT52BR3224AT
AT52BR3228A
AT52BR3228AT
Flash Boot
Location
Bottom
Top
Bottom
Top
Flash Plane
Architecture
32M
32M
32M
32M
SRAM
Configuration
256K x 16
256K x 16
512K x 16
512K x 16
Preliminary
Rev. 3338B–STKD–6/03
1
Pin Configuration
Pin Name
A0 - A17
A0 - A18
A19 - A20
CE
OE
WE
RESET
RDY/BUSY
VPP
VCC
GND
I/O0 - I/O15
NC
SLB
SUB
SVCC
SGND
SCS1
SCS2
SWE
SOE
Function
Flash/SRAM Common Address Input for 4M SRAM
Flash/SRAM Common Address Input for 8M SRAM
Flash Address Input
Flash Chip Enable
Flash Output Enable
Flash Write Enablee
Flash Reset
Flash READY/BUSY Output
Flash Power Supply for Accelerated Program/Erase Operations
Flash Power
Flash Ground
Data Inputs/Outputs
No Connect
SRAM Lower Byte
SRAM Upper Byte
SRAM Power
SRAM Ground
SRAM Chip Select 1
SRAM Chip Select 2
SRAM Write Enable
SRAM Output Enable
AT52BR3224A(T)/
AT52BR3228A(T)
(Top View)
A
B
1
2
3
4
5
6
7
8
9
10
11
12
NC
NC
A20
A16
A11
A8
A15
A10
A14
A9
A13
A12
GND
NC
I/O7
I/O5
NC
NC
I/O15 SWE I/O14
I/O13
I/O6
I/O4
C
WE
RDY/BUSY
D
SGND
RES
I/O12 SCS2 SVCC VCC
A19
SOE
A7
A4
A6
A0
I/O11
I/O9
A3
CE
I/O10
I/O8
A2
GND
I/O2
I/O0
A1
OE
I/O3
I/O1
SCS1
NC
NC
NC
E
NC
VPP
SUB
A17
A5
F
SLB
G
A18
H
NC
NC
NC
2
AT52BR3224A(T)/3228A(T)
3338B–STKD–6/03
AT52BR3224A(T)/3228A(T)
Block Diagram
ADDRESS
OE WE
SOE SWE
RESET
CE
RDY/BUSY
32-Mbit
FLASH
4/8-Mbit
SRAM
SCS1
SCS2
DATA
Description
The AT52BR3224A(T) combines a 32-megabit Flash (2M x 16) and a 4-megabit SRAM (orga-
nized as 256K x 16) in a stacked 66-ball CBGA package. The AT52BR3228A(T) combines a
32-megabit Flash (2M x 16) and an 8-megabit SRAM (organized as 512K x 16) in a stacked
66-ball CBGA package. The stacked modules operate at 2.7V to 3.3V in the industrial temper-
ature range.
Absolute Maximum Ratings
Temperature under Bias.................................. -40° C to +85° C
Storage Temperature .................................... -55° C to +150° C
All Input Voltages
except V
PP
and RESET
(including NC Pins)
with Respect to Ground .....................................-0.2V to +3.3V
Voltage on V
PP
with Respect to Ground ..................................-0.2V to + 6.25V
Voltage on RESET
with Respect to Ground ...................................-0.2V to +13.5V
All Output Voltages
with Respect to Ground .....................................-0.2V to +0.2V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
DC and AC Operating Range
AT52BR3224A(T)/3228A(T)-70
Operating Temperature (Case)
V
CC
Power Supply
Industrial
-40° C - 85° C
2.7V to 3.3V
3
3338B–STKD–6/03
32-megabit
Flash Memory
Description
The 32-megabit Flash is a a 2.7-volt memory organized as 2,097,152 words of 16 bits each.
The memory is divided into 71 sectors for erase operations. The device has CE and OE con-
trol signals to avoid any bus contention. This device can be read or reprogrammed using a
single power supply, making it ideally suited for in-system programming.
The device powers on in the read mode. Command sequences are used to place the device in
other operation modes such as program and erase. The device has the capability to protect
the data in any sector (see “Sector Lockdown” section).
To increase the flexibility of the device, it contains an Erase Suspend and Program Suspend
feature. This feature will put the erase or program on hold for any amount of time and let the
user read data from or program data to any of the remaining sectors within the memory. The
end of a program or an erase cycle is detected by the READY/BUSY pin, Data Polling or by
the toggle bit.
The VPP pin provides data protection. When the V
PP
input is below 0.4V, the program and
erase functions are inhibited. When V
PP
is at 0.9V or above, normal program and erase opera-
tions can be performed.
A six-byte command (Enter Single Pulse Program Mode) sequence to remove the requirement
of entering the three-byte program sequence is offered to further improve programming time.
After entering the six-byte code, only single pulses on the write control lines are required for
writing into the device. This mode (Single Pulse Word Program) is exited by powering down
the device, or by pulsing the RESET pin low for a minimum of 500 ns and then bringing it back
to V
CC
. Erase, Erase Suspend/Resume and Program Suspend/Resume commands will not
work while in this mode; if entered they will result in data being programmed into the device. It
is not recommended that the six-byte code reside in the software of the final product but only
exist in external programming code.
4
AT52BR3224A(T)/3228A(T)
3338B–STKD–6/03
AT52BR3224A(T)/3228A(T)
Block Diagram
I/O0 - I/O15
OUTPUT
BUFFER
INPUT
BUFFER
OUTPUT
MULTIPLEXER
A0 - A20
INPUT
BUFFER
STATUS
REGISTER
DATA
REGISTER
IDENTIFIER
REGISTER
COMMAND
REGISTER
ADDRESS
LATCH
DATA
COMPARATOR
CE
WE
OE
RESET
RDY/BUSY
WRITE STATE
MACHINE
Y-DECODER
Y-GATING
PROGRAM/ERASE
VOLTAGE SWITCH
VPP
VCC
GND
X-DECODER
MAIN
MEMORY
5
3338B–STKD–6/03
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