AT52BR3224A-70CI datasheet, PDF

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AT52BR3224A-70CI: Description32-megabit Flash + 4-megabit/ 8-megabit SRAM Stack Memory; Categorystorage storage; File Size345KB，46 Pages; ManufacturerAtmel (Microchip)

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AT52BR3224A-70CI Overview

32-megabit Flash + 4-megabit/ 8-megabit SRAM Stack Memory

AT52BR3224A-70CI Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Atmel (Microchip)
Parts packaging code	BGA
package instruction	TFBGA, BGA66,8X12,32
Contacts	66
Reach Compliance Code	compliant
Maximum access time	70 ns
Other features	SRAM IS ORGANISED AS 256K X 16
JESD-30 code	R-PBGA-B66
JESD-609 code	e0
length	10 mm
memory density	33554432 bit
Memory IC Type	MEMORY CIRCUIT
memory width	16
Mixed memory types	FLASH+SRAM
Humidity sensitivity level	3
Number of functions	1
Number of terminals	66
word count	2097152 words
character code	2000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	2MX16
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Encapsulate equivalent code	BGA66,8X12,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	240
power supply	3 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum standby current	0.000006 A
Maximum slew rate	0.015 mA
Maximum supply voltage (Vsup)	3.3 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	8 mm
Base Number Matches	1

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Features

•

32-Mbit Flash and 4-Mbit/8-Mbit SRAM

•

Single 66-ball (8 mm x 10 mm x 1.2 mm) CBGA Package

•

2.7V to 3.3V Operating Voltage

Flash

•

2.7V to 3.3V Read/Write

•

Access Time – 70 ns

•

Sector Erase Architecture

•

– Sixty-three 32K WordSectors with Individual Write Lockout

– Eight 4K Word Sectors with Individual Write Lockout

Fast Word Program Time – 15 µs

Sector Erase Time – 300 ms

Suspend/Resume Feature for Erase and Program

– Supports Reading and Programming from Any Sector by Suspending Erase of a

Different Sector

– Supports Reading Any Word by Suspending Programming of Any Other Word

Low-power Operation

– 12 mA Active

– 13 µA Standby

Data Polling, Toggle Bit, Ready/Busy for End of Program Detection

VPP Pin for Write Protection and Accelerated Program/Erase Operations

RESET Input for Device Initialization

Sector Lockdown Support

Top or Bottom Boot Block Configuration Available

128-bit Protection Register

Minimum 100,000 Erase Cycles

•

32-megabit

Flash

+ 4-megabit/

8-megabit

SRAM

Stack Memory

AT52BR3224A

AT52BR3224AT

AT52BR3228A

AT52BR3228AT

SRAM

•

4-megabit (256K x 16)/8-megabit (512K x 16)

2.7V to 3.3V V

70 ns Access Time

Fully Static Operation and Tri-state Output

1.2V (Min) Data Retention

Industrial Temperature Range

Device Number

AT52BR3224A

AT52BR3224AT

AT52BR3228A

AT52BR3228AT

Flash Boot

Location

Bottom

Top

Bottom

Top

Flash Plane

Architecture

32M

SRAM

Configuration

256K x 16

512K x 16

Preliminary

Rev. 3338B–STKD–6/03

32-megabit

Flash Memory

Description

The 32-megabit Flash is a a 2.7-volt memory organized as 2,097,152 words of 16 bits each.

The memory is divided into 71 sectors for erase operations. The device has CE and OE con-

trol signals to avoid any bus contention. This device can be read or reprogrammed using a

single power supply, making it ideally suited for in-system programming.

The device powers on in the read mode. Command sequences are used to place the device in

other operation modes such as program and erase. The device has the capability to protect

the data in any sector (see “Sector Lockdown” section).

To increase the flexibility of the device, it contains an Erase Suspend and Program Suspend

feature. This feature will put the erase or program on hold for any amount of time and let the

user read data from or program data to any of the remaining sectors within the memory. The

end of a program or an erase cycle is detected by the READY/BUSY pin, Data Polling or by

the toggle bit.

The VPP pin provides data protection. When the V

input is below 0.4V, the program and

erase functions are inhibited. When V

is at 0.9V or above, normal program and erase opera-

tions can be performed.

A six-byte command (Enter Single Pulse Program Mode) sequence to remove the requirement

of entering the three-byte program sequence is offered to further improve programming time.

After entering the six-byte code, only single pulses on the write control lines are required for

writing into the device. This mode (Single Pulse Word Program) is exited by powering down

the device, or by pulsing the RESET pin low for a minimum of 500 ns and then bringing it back

to V

. Erase, Erase Suspend/Resume and Program Suspend/Resume commands will not

work while in this mode; if entered they will result in data being programmed into the device. It

is not recommended that the six-byte code reside in the software of the final product but only

exist in external programming code.

AT52BR3224A(T)/3228A(T)

3338B–STKD–6/03

AT52BR3224A-70CI Related Products

	AT52BR3224A-70CI	AT52BR3224AT-70CI	AT52BR3228A	AT52BR3224A	AT52BR3228AT	AT52BR3224AT	AT52BR3228AT-70CI	AT52BR3228A-70CI
Description	32-megabit Flash + 4-megabit/ 8-megabit SRAM Stack Memory	32-megabit Flash + 4-megabit/ 8-megabit SRAM Stack Memory	32-megabit Flash + 4-megabit/ 8-megabit SRAM Stack Memory	32-megabit Flash + 4-megabit/ 8-megabit SRAM Stack Memory	32-megabit Flash + 4-megabit/ 8-megabit SRAM Stack Memory	32-megabit Flash + 4-megabit/ 8-megabit SRAM Stack Memory	32-megabit Flash + 4-megabit/ 8-megabit SRAM Stack Memory	32-megabit Flash + 4-megabit/ 8-megabit SRAM Stack Memory

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