Features
•
•
•
•
•
Available in Gate Array or Embedded Array
High-speed, 100 ps Gate Delay, 2-input NAND, FO = 2 (nominal)
Up to 6.9 Million Used Gates and 976 Pins
0.25µ Geometry in up to Five-level Metal
System-level Integration Technology
– Cores: ARM7TDMI
™
, ARM920T
™
, ARM946E-S
™
and MIPS64
™
5Kf
™
RISC
Microprocessors; AVR
®
RISC Microcontroller; OakDSPCore
™
, Teak
™
and
PalmDSPCore
™
Digital Signal Processors; 10/100 Ethernet MAC, USB, 1394, 1284,
CAN and Other Assorted Processor Peripherals
– Analog Functions: DACs, ADCs, OPAMPs, Comparators, PLLs and PORs
– Soft Macro Memory: Gate Array
SRAM — ROM — DPSRAM — FIFO
– Hard Macro Memory: Embedded Array
SRAM — ROM — DPSRAM — FIFO — Stacked E
2
— Stacked Flash
– I/O Interfaces: CMOS, LVTTL, LVDS, PCI, USB; Output Currents up to 16 mA
@2.5V; 2.5V Native I/O, 3.3V Tolerant/Compliant I/O, 5.0V Tolerant I/O
ASIC
ATL25 Series
Description
The ATL25 Series ASIC family is fabricated on a 0.25µ CMOS process with up to five
levels of metal. This family features arrays with up to 6.9 million routable gates and
976 pins. The high density and high pin count capabilities of the ATL25 family, coupled
with the ability to add embedded microprocessor cores, DSP engines and memory on
the same silicon, make the ATL25 series of ASICs an ideal choice for system-level
integration.
Figure 1.
ATL25 Gate Array ASIC
Standard
Gate Array
Architecture
Figure 2.
ATL25 Embedded Array ASIC
Standard
Gate Array
Architecture
Analog
1414C–ASIC-08/02
1
Table 1.
ATL25 Array Organization
Device
Number
ATL25/44
ATL25/68
ATL25/84
ATL25/100
ATL25/120
ATL25/132
ATL25/144
ATL25/160
ATL25/184
ATL25/208
ATL25/228
ATL25/256
ATL25/304
ATL25/352
ATL25/388
ATL25/432
ATL25/484
ATL25/540
ATL25/600
ATL25/700
ATL25/800
ATL25/900
ATL25/976
Notes:
4LM Routable
Gates
(1)
9,535
30,096
50,410
75,472
106,278
131,670
159,778
200,998
270,663
329,281
401,010
512,398
733,635
925,815
1,133,594
1,417,125
1,651,406
2,069,052
2,567,790
3,520,954
4,231,979
5,378,257
5,765,320
5LM Routable
Gates
(1)
10,727
33,858
56,712
84,906
120,449
149,226
181,081
227,797
306,751
376,321
458,298
585,598
838,440
1,068,248
1,307,994
1,635,145
1,926,640
2,413,894
2,995,755
4,107,780
5,001,430
6,356,122
6,918,384
Available
Routing Sites
(2)
15,892
50,161
84,018
125,788
188,940
234,080
284,050
357,330
481,179
627,203
763,830
975,998
1,397,400
1,899,108
2,325,323
2,906,925
3,669,792
4,597,895
5,706,200
7,824,344
10,259,344
13,038,200
15,374,188
Max Pad
Count
44
68
84
100
120
132
144
160
184
208
228
256
304
352
388
432
484
540
600
700
800
900
976
Max I/O Count
36
60
76
92
112
124
136
152
176
200
220
248
296
344
380
424
476
532
592
692
792
892
968
Gate
Speed
(3)
100 ps
100 ps
100 ps
100 ps
100 ps
100 ps
100 ps
100 ps
100 ps
100 ps
100 ps
100 ps
100 ps
100 ps
100 ps
100 ps
100 ps
100 ps
100 ps
100 ps
100 ps
100 ps
100 ps
1. One gate = NAND2
2. Routing site = 4 transistors
3. Nominal 2-input NAND gate FO = 2 at 2.5V
2
ATL25 Series ASIC
1414C–ASIC-08/02
ATL25 Series ASIC
Design
Atmel supports several major software systems for design with complete cell libraries, as well
as utilities for netlist verification, test vector verification and accurate delay simulations
Table 2.
Design Systems Supported
System
Cadence
®
Design
Systems, Inc.
Tools
Opus
™
– Schematic and Layout
NC Verilog
™
– Verilog Simulator
Pearl
™
– Static Path
Verilog-XL
™
– Verilog Simulator
BuildGates
™
– Synthesis (Ambit)
ModelSim
®
– Verilog and VHDL (VITAL) Simulator
Leonardo Spectrum
™
– Logic Synthesis
Design Compiler
™
– Synthesis
DFT Compiler – 1-Pass Test Synthesis
BSD Compiler – Boundary Scan Synthesis
TetraMax
®
– Automatic Test Pattern Generation
PrimeTime
™
– Static Path
VCS
™
– Verilog Simulator
Floorplan Manager
™
Debussy
®
First Encounter
®
Version
4.46
3.3-s008
4.3-s095
3.3-s006
4.0-p003
5.5e
2001.1d
01.01-SP1
01.08-SP1
01.08-SP1
01.08
01.08-SP1
5.2
01.08-SP1
5.1
v2001.2.3
Mentor
Graphics
®
Synopsys
®
Novas
Software, Inc.
®
Silicon
Perspective
™
Atmel’s ASIC design flow is structured to allow the designer to consolidate the greatest num-
ber of system components onto the same silicon chip, using widely available third-party design
tools. Atmel’s cell library reflects silicon performance over extremes of temperature, voltage
and process, and includes the effects of metal loading, interlevel capacitance, and edge rise
and fall times. The design flow includes clock tree synthesis to customer-specified skew and
latency goals. RC extraction is performed on the final design database and incorporated into
the timing analysis.
The ASIC design flow, shown on page 4, provides a pictorial description of the typical interac-
tion between Atmel’s design staff and the customer. Atmel will deliver design kits to support
the customer’s synthesis, verification, floorplanning and scan insertion activities. Leading-
edge tools from vendors such as Synopsys and Cadence are fully supported in our design
flow. In the case of an embedded array design, Atmel will conduct a design review with the
customer to define the partition of the embedded array ASIC and to define the location of the
memory blocks and/or cores so an underlayer layout model can be created.
Following database acceptance, automated test pattern generation (ATPG) is performed, if
required, on scan paths using Synopsys tools; the design is routed; and post-route RC data is
extracted. After post-route verification and a final design review, the design is taped out for
fabrication.
3
1414C–ASIC-08/02
Table 3.
Design Flow
Deliver
Design Kit
Kickoff
Meeting
If Embedded Array
Define
Underlayer
Synthesis/
Design Entry
Scan/JTAG
Simulation/
Static Path
Floorplan
If Embedded Array
(Preliminary Netlist)
Create
Underlayer
Database
Handoff
Tape Out
Underlayer
Database
Acceptance
Fabricate
Underlayer
Place and Route/
Clock Tree
Verification/
Resimulation
Final Design
Review
If Standard Cell
If Embedded/Gate Array
Tape Out
Full Mask Set
Tape Out
Metal Masks
Fabricate
Fabricate
Personality
Customer
Atmel
Joint
Proto Assembly
and Test
Rev. 2.2-03/02
Proto Shipment
4
ATL25 Series ASIC
1414C–ASIC-08/02
ATL25 Series ASIC
Pin Definition
Requirements
The corner pads are reserved for power and ground only. All other pads are fully programma-
ble as input, output, bidirectional, power, or ground. When implementing a design with 3.3V
compliant buffers, an appropriate number of pad sites must be reserved for the V
DD
3 pins,
which are used to distribute 3.3V power to the compliant buffers.
Design Options
Logic Synthesis
Atmel can accept RTL designs in Verilog or VHDL HDL formats. Atmel fully supports Synop-
sys for Verilog or VHDL simulation as well as synthesis. Of the two HDL formats, Verilog and
VHDL, Atmel’s preferred HDL format for ASIC design is Verilog.
Atmel has successfully translated existing designs from most major ASIC vendors into Atmel
ASICs. These designs have been optimized for speed and gate count and modified to add
logic or memory, or replicated as a pin-for-pin compatible, drop-in replacement.
Atmel has successfully translated existing FPGA/PLD designs from most major vendors into
Atmel ASICs. There are four primary reasons to convert from an FPGA/PLD to an ASIC:
•
•
•
•
Conversion of high-volume devices for a single or combined design is cost effective.
Performance can often be optimized for speed or low power consumption.
Several FPGA/PLDs can be combined onto a single chip to minimize cost while reducing
on-board space requirements.
In situations where an FPGA/PLD was used for fast cycle time prototyping, an ASIC may
provide a lower cost answer for long-term volume production.
ASIC Design
Translation
FPGA and PLD
Conversions
5
1414C–ASIC-08/02
Analog electronics
京公网安备 11010802033920号
EEWORLD
