Features
•
Single-chip All-in-one Design, Only Requires External DAC
– MIDI Control Processor, Serial and Parallel Interface
– Synthesis, General MIDI Wavetable Implementation
– Compatible Effects: Reverb + Chorus
– Spatial Effect
– 4-band Stereo Equalizer
State-of-the-art Synthesis for Best Quality/Price Products
– 38-voice Polyphony + Effects
– On-chip CleanWave
™
Wavetable Data, Firmware, RAM Delay Lines
Synthesizer Chipset: ATSAM2193/ATSAM2193-G + DAC
Hardware Programmable DAC Mode
– I2S: 16 to 20 bits
– Japanese: 16 bits
Typical Applications
– Battery-operated Musical Keyboards
– Portable Phones
– Karaokes
TQFP44 (10 mm x 10 mm) Package for ATSAM2193
TFBGA44 (7 mm x 7 mm) Package for ATSAM2193-G
– Both Options Provide Small Footprint, Low Pin Count
Low-power
– 95 mW Typical Operating, <5 µA Power-down
– 2.5V and 3.3V Power Supply or Single 2.5V Supply
– Built-in Power Switch
•
•
•
•
Sound
Synthesis
ATSAM2193
ATSAM2193-G
Low-power
Single-chip
Synthesizer
with Effects
•
•
Description
The ATSAM2193 provides a single-chip, low-cost MIDI sound system. Equipped with
a serial and a parallel MIDI input, it provides state-of-the-art sound synthesis using a
full GM sound set together with a range of compatible effects. Its low power consump-
tion makes it ideal for all battery-powered applications such as portable Karaoke or
any other device using MIDI synthesis.
The ATSAM2193-G has the same functionality as the ATSAM2193 but is presented in
a TFBGA44 package.
Figure 1.
Typical Hardware Configuration
MIDI IN
MPU-401
(Parallel MIDI)
ATSAM2193
or
ATSAM2193-G
Stereo
DAC
Audio
Out
Rev. 2695A–DRMSD–06/03
1
Pin Description
44-lead TQFP Package
Table 1.
Pin by Function - 44-lead TQFP Package
Pin Name
Pin Number
Type
Function
Power Supply Group
GND
VC3
VC2
9, 11, 20, 22,
30, 34, 38, 42
10, 29
1, 12, 32, 41,
44
35
PWR
PWR
PWR
Digital ground - all pins should be connected to a ground plane.
I/O power supply, 2.25V to 3.6V. All pins should be connected to a nominal 3.3V power.
Core power supply, 2.25V to 2.75V. All pins should be connected to nominal 2.5V. If the
built-in power switch is used for minimum power-down consumption, then all these pins
should be connected to the output of the power switch PWROUT (pin 36).
Power switch input, 2.25V to 2.95V. Even if the power switch feature is not used, this pin
must be connected to nominal 2.5V.
PWRIN
PWR
Serial MIDI, Parallel MIDI (MPU-401)
MIDI IN
17
IN
Serial TTL MIDI IN. Connected to the built-in synthesizer at power-up or after MPU reset.
Connected to the D0 - D7 bus (read mode) when MPU switched to UART mode. This pin
should be tied HIGH if not used.
8-bit bi-directional bus, under control of CS, RD, WR. These pins should be left
unconnected if not used.
This pin has built-in pull-down. Should be left unconnected if not used.
Select:
0 = data registers (read/write)
1 = status register (read), control register (write)
Chip select, active low. This pin has a built-in pull-down. It should be left unconnected if not
used.
Read, active low. When CS and RD are low, data (A0 = 0) or status (A0 = 1) is read on D0-
D7. Read data is acknowledged on the rising edge of RD. This pin has a built-in pull-down.
It should be left unconnected if not used.
Write, active low. When CS and WR are low, data (A0 = 0) or control (A0 = 1) is written from
the D0 -D7 bus to the ATSAM2193 on the rising edge of WR. This pin has a built-in pull-up.
It should be left unconnected if not used.
A rising edge indicates that a MIDI byte is available for read on D0 - D7. Acknowledged by
reading the byte.
D0 - D7
A0
6, 8, 14, 16,
18, 21, 24, 26
2
I/O
IN
CS
RD
4
31
IN
IN
WR
33
IN
IRQ
28
OUT
Digital Audio Group
CLBD
WSBD
DABD
DACSEL
3
23
27
15
OUT
OUT
OUT
IN
Digital audio bit clock.
Digital audio left/right select.
Digital audio stereo output.
DAC type:
0 = I2S 16 to 20 bits
1 = Japanese 16 bits
Miscellaneous Group
X1, X2
39, 40
-
9.6 MHz crystal connection. An external 9.6 MHz clock can also be used on X1 (2.5V
PP
max through 47 pF capacitor). X2 cannot be used to drive external circuits, use CKOUT
instead.
2
ATSAM2193/ATSAM2193-G
2695A–DRMSD–06/03
ATSAM2193/ATSAM2193-G
Table 1.
Pin by Function - 44-lead TQFP Package (Continued)
Pin Name
CKOUT
LFT
RESET
PWROUT
PDWN
Pin Number
7
43
5
36
37
Type
OUT
-
IN
PWR
IN
Function
Buffered X2 output, can be used to drive external DAC master clock (256 * Fs)
PLL external RC network.
Reset input, active low. This is a Schmitt trigger input, allowing direct connection to an RC
network.
Power switch output. Use this pin to supply 2.5V nominal core voltage by connecting it to all
V
C2
pins.
Power down, active low. When power down is active, all outputs are set to logic level 0. The
PLL and crystal oscillator are stopped. If the power switch feature is used, then 2.5V supply
is removed from the core. To exit from power down, PDWN must be set to V
C2
, then RESET
applied. When unused this pin must be connected to V
C2
.
Test pins, should be grounded.
When high, indicates synthesizer is up and running.
TEST0 -
TEST1
RUN
13, 25
19
IN
OUT
Table 2.
Pinout by Pin Number - 44-lead TQFP Package
Pin Number
1
2
3
4
5
6
7
8
9
10
11
Signal Name
VC2
A0
CLBD
CS
RESET
D0
CKOUT
D1
GND
VC3
GND
Pin Number
12
13
14
15
16
17
18
19
20
21
22
Signal Name
VC2
TEST0
D2
DACSEL
D3
MIDI IN.
D4
RUN
GND
D5
GND
Pin Number
23
24
25
26
27
28
29
30
31
32
33
Signal Name
WSBD
D6
TEST1
D7
DABD
IRQ
VC3
GND
RD
VC2
WR
Pin Number
34
35
36
37
38
39
40
41
42
43
44
Signal Name
GND
PWRIN
PWROUT
PDWN
GND
X1
X2
VC2
GND
LFT
VC2
3
2695A–DRMSD–06/03
44-ball TFBGA Package
Table 3.
Pin by Function - 44-ball TFBGA Package
Pin Name
Pin Number
Type
Function
Power Supply Group
GND
A4, B4, C3,
C5, E3, E5,
G2, G6
A7, D1
D6, F2, F4, F7,
G5
F1
PWR
Digital ground - all pins should be connected to a ground plane.
VC3
VC2
PWR
PWR
I/O power supply, 2.25V to 3.6V. All pins should be connected to a nominal 3.3V power.
Core power supply, 2.25V to 2.75V. All pins should be connected to nominal 2.5V. If the
built-in power switch is used for minimum power-down consumption, then all these pins
should be connected to the output of the power switch PWROUT (pin 36).
Power switch input, 2.25V to 2.95V. Even if the power switch feature is not used, this pin
must be connected to nominal 2.5V.
PWRIN
PWR
Serial MIDI, Parallel MIDI (MPU-401)
MIDI IN
B5
IN
Serial TTL MIDI IN. Connected to the built-in synthesizer at power-up or after MPU reset.
Connected to the D0 - D7 bus (read mode) when MPU switched to UART mode. This pin
should be tied HIGH if not used.
8-bit bi-directional bus, under control of CS, RD, WR. These pins should be left
unconnected if not used.
This pin has built-in pull-down. Should be left unconnected if not used.
Select:
0 = data registers (read/write)
1 = status register (read), control register (write)
Chip select, active low. This pin has a built-in pull-down. It should be left unconnected if not
used.
Read, active low. When CS and RD are low, data (A0 = 0) or status (A0 = 1) is read on D0-
D7. Read data is acknowledged on the rising edge of RD. This pin has a built-in pull-down.
It should be left unconnected if not used.
Write, active low. When CS and WR are low, data (A0 = 0) or control (A0 = 1) is written from
the D0 -D7 bus to the ATSAM2193 on the rising edge of WR. This pin has a built-in pull-up.
It should be left unconnected if not used.
A rising edge indicates that a MIDI byte is available for read on D0 - D7. Acknowledged by
reading the byte.
D0 - D7
D7, C7, B6,
A5, B3, A2, B1,
C1
F5
I/O
A0
IN
CS
RD
E6
E2
IN
IN
WR
G1
IN
IRQ
D2
OUT
Digital Audio Group
CLBD
WSBD
DABD
DACSEL
F6
A1
C2
A6
OUT
OUT
OUT
IN
Digital audio bit clock.
Digital audio left/right select.
Digital audio stereo output.
DAC type:
0 = I2S 16 to 20 bits
1 = Japanese 16 bits
Miscellaneous Group
X1, X2
G3, G4
-
9.6 MHz crystal connection. An external 9.6 MHz clock can also be used on X1 (2.5V
PP
max through 47 pF capacitor). X2 cannot be used to drive external circuits, use CKOUT
instead.
4
ATSAM2193/ATSAM2193-G
2695A–DRMSD–06/03
ATSAM2193/ATSAM2193-G
Table 3.
Pin by Function - 44-ball TFBGA Package (Continued)
Pin Name
CKOUT
LFT
RESET
PWROUT
PDWN
Pin Number
C6
G7
E7
E1
F3
Type
OUT
-
IN
PWR
IN
Function
Buffered X2 output, can be used to drive external DAC master clock (256 * Fs)
PLL external RC network.
Reset input, active low. This is a Schmitt trigger input, allowing direct connection to an RC
network.
Power switch output. Use this pin to supply 2.5V nominal core voltage by connecting it to all
V
C2
pins.
Power down, active low. When power down is active, all outputs are set to logic level 0. The
PLL and crystal oscillator are stopped. If the power switch feature is used, then 2.5V supply
is removed from the core. To exit from power down, PDWN must be set to V
C2
, then RESET
applied. When unused this pin must be connected to V
C2
.
Test pins, should be grounded.
When high, indicates synthesizer is up and running.
TEST0 -
TEST1
RUN
B7, B2
A3
IN
OUT
Figure 2.
Pinout by Pin Coordinate - 44-ball TFBGA (Top View)
WSBD
D5
RUN
GND
D3
DACSEL VC3
D6
TEST1
D4
GND MIDI IN
D2
TEST0
D7
DABD
GND
GND CKOUT
D1
VC3
IRQ
VC2
D0
PWROUT
RD
GND
GND
CS
RESET
PWRIN VC2
WR
GND
PDWN
X1
VC2
X2
A0
VC2
CLBD
GND
VC2
LFT
5
2695A–DRMSD–06/03
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