The OPA687 combines a very high gain bandwidth and
large signal performance with an ultra-low input noise
voltage (0.95nV/√Hz) while dissipating only 18mA sup-
ply current. Where power savings is paramount, the
OPA687 also includes an optional power down pin that,
when pulled low, will disable the amplifier and decrease
the quiescent current to only 1% of its powered up value.
This optional feature may be left disconnected to insure
normal amplifier operation when no power-down is re-
quired.
The combination of low input voltage and current noise,
along with a 3.8GHz gain bandwidth product, make the
OPA687 an ideal amplifier for wideband transimpedance
+5V
V
CM
100Ω
OPA687
20Ω
stages. As a voltage gain stage, the OPA687 is opti-
mized for a flat frequency response at a gain of +20 and
is guaranteed stable down to gains of +12. New external
compensation techniques allows the OPA687 to be used
at any inverting gain with excellent frequency response
control. Using this compensation can give an extremely
high dynamic range ADC driver to support > 40MSPS
12- and 14-bit converters.
OPA687 RELATED PRODUCTS
SINGLES
OPA642
OPA643
OPA686
DUAL
INPUT NOISE
VOLTAGE (nV/√Hz)
2.7
2.3
1.3
GAIN BANDWIDTH
PRODUCT (MHz)
210
800
1600
OPA2686
+5V
–60
50Ω Source
–5V
V
IN
+
80pF
850Ω
ADS852
14-Bit
65MSPS
3rd-Order Spurious (dBc)
1.7pF
39pF
–65
4Vp-p
–70
1:2
< 6dB
Noise
Figure
39pF
850Ω
–75
2Vp-p
+5V
100Ω
OPA687
V
CM
1.7pF
20Ω
80pF
V
IN
–
–80
–85
0
5
10
15
20
25
30
35
40
45
50
Center Frequency (MHz)
–5V
Ultra-High Dynamic Range
Differential Input ADC Driver
Measured 2-Tone, 3rd-Order Distortion for
Differential ADC Driver.
IInternational Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
= 39.2Ω, G = +20 (Figure 1 for AC performance only), unless otherwise noted.
OPA687U, N
TYP
+25
°
C
600
290
75
3800
35
3
–74
–95
–108
–110
43
0.95
2.5
1.2
900
17
15
8
85
±0.1
–20
±0.2
+25
°
C
(2)
GUARANTEED
0
°
C to
70
°
C
(3)
–40
°
C to
+85
°
C
(3)
MIN/ TEST
MAX LEVEL
(1)
typ
min
min
min
min
max
max
max
max
max
min
max
max
max
min
typ
max
max
min
max
max
max
max
max
max
min
min
typ
typ
min
min
min
min
typ
typ
max
max
min
min
max
min
max
max
typ
typ
typ
typ
typ
typ
C
B
B
B
B
B
B
B
B
B
B
B
B
B
B
C
B
B
A
A
B
A
B
A
B
A
A
C
C
A
A
A
A
C
C
A
A
A
A
A
A
A
A
C
C
C
C
C
C
PARAMETER
AC PERFORMANCE (Figure 1)
Closed-Loop Bandwidth
CONDITIONS
G = +12, R
G
= 39.2Ω, V
O
= 200mVp-p
G = +20, R
G
= 39.2Ω, V
O
= 200mVp-p
G = +50, R
G
= 39.2Ω, V
O
= 200mVp-p
G
≥
+50
G = +20, R
L
= 100Ω
G = +20, f = 5MHz, V
O
= 2Vp-p
R
L
= 100Ω
R
L
= 500Ω
R
L
= 100Ω
R
L
= 500Ω
G = +20, f = 20MHz
f > 1MHz
f > 1MHz
0.2V Step
2V Step
2V Step
2V Step
2V Step
V
O
= 0V
V
CM
= 0V
V
CM
= 0V
V
CM
= 0V
V
CM
= 0V
V
CM
= 0V
V
CM
= 0V
UNITS
MHz
MHz
MHz
MHz
MHz
dB
dBc
dBc
dBc
dBc
dBm
nV/√Hz
pA/√Hz
ns
V/µs
ns
ns
ns
dB
mV
µV/°C
µA
nA/°C
µA
nA/°C
V
dB
kΩ || pF
MΩ || pF
Gain Bandwidth Product
Bandwidth for 0.1dB Gain Flatness
Peaking at a Gain of +12
Harmonic Distortion
2nd Harmonic
3rd Harmonic
Two-Tone, 3rd-Order Intercept
Input Voltage Noise Density
Input Current Noise Density
Pulse Response
Rise/Fall Time
Slew Rate
Settling Time to 0.01%
0.1%
1%
DC PERFORMANCE
(4)
Open-Loop Voltage Gain (A
OL
)
Input Offset Voltage
Average Offset Voltage Drift
Input Bias Current
Input Bias Current Drift (magnitude)
Input Offset Current
Input Offset Current Drift
INPUT
Common-Mode Input Range (CMIR)
(5)
Common-Mode Rejection Ratio (CMRR)
Input Impedance
Differential
Common-Mode
OUTPUT
Output Voltage Swing
Current Output, Sourcing
Current Output, Sinking
Closed-Loop Output Impedance
POWER SUPPLY
Specified Operating Voltage
Maximum Operating Voltage
Quiescent Current, max
Quiescent Current, min
Power Supply Rejection Ratio
+PSRR, –PSRR
POWER-DOWN (Disabled Low)
Power-Down Quiescent Current (+V
S
)
On Voltage (Enabled High or Floated)
Off Voltage (Disabled Asserted Low)
Power-Down Pin Input Bias Current
Power-Down Time
Power-Up Time
Off Isolation
THERMAL
Specification U, N
Thermal Resistance,
θ
JA
U 8-Pin, SO-8
N 6-Pin, SOT23
180
60
3000
24
8
–70
–90
–95
–105
40
1.1
3.2
2.0
675
18
11
78
160
54
2700
20
10
–68
–88
–90
–100
39
1.15
3.3
2.2
550
20
13
75
±1.2
5
–36
–50
±1.5
±12
±2.9
83
140
48
2400
18
14
–65
–85
–85
–95
37
1.3
3.5
2.5
450
25
17
70
±1.6
10
–40
–100
±1.8
±15
±2.8
78
±
1
–33
±
1.0
±
3.0
88
V
CM
=
±0.5V,
Input Referred
V
CM
= 0V
V
CM
= 0V
≥
400Ω Load
100Ω Load
V
O
= 0V
V
O
= 0V
G = +20, f = < 100kHz
±3.2
100
2.5 || 2.5
1.0 || 1.2
±3.6
±3.5
80
–80
0.006
±5
±6
18.5
18.5
85
–225
3.3
1.8
100
200
60
70
–40 to +85
±
3.3
±
3.2
60
–60
±3.1
±2.9
50
–50
±3.0
±2.8
40
–40
V
V
mA
mA
Ω
V
V
mA
mA
dB
µA
V
V
µA
ns
ns
dB
°C
V
S
=
±5V
V
S
=
±5V
|V
S
| = 4.5V to 5.5V, Input Referred
(Pin 8 SO-8; Pin 5 on SOT23-6)
±
6
19
18
80
–300
3.5
1.7
160
±6
19.5
17.5
78
–350
3.6
1.6
160
±6
20.5
16
75
–400
3.7
1.5
160
(V
DIS
= 0)
5MHz, Input to Output
Junction to Ambient
125
150
°C/W
°C/W
NOTES: (1) Test Levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation.
(C) Typical value only for information. (2) Junction temperature = ambient for +25°C guaranteed specifications. (3) Junction temperature = ambient at low temperature
limit: junction temperature = ambient +23°C at high temperature limit for over temperature guaranteed specifications. (4) Current is considered positive out of node. V
CM
is the input common-mode voltage. (5) Tested <3dB below minimum specified CMRR at
±CMIR
limits.
®
OPA687
2
ABSOLUTE MAXIMUM RATINGS
Power Supply ................................................................................
±6.5V
DC
Internal Power Dissipation ...................................... See Thermal Analysis
Differential Input Voltage ..................................................................
±1.2V
Input Voltage Range ............................................................................
±V
S
Storage Temperature Range: U, N ................................. –40°C to +125°C
Lead Temperature (soldering, 10s) ............................................... +300°C
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
PIN CONFIGURATION
Top View
SO-8
Top View
OPA687
Output
1
6
+V
S
SOT23-6
OPA687
–V
S
2
5
DIS
NC
1
8
DIS
Noninverting Input
3
4
Inverting Input
Inverting Input
2
7
+V
S
Noninverting Input
3
6
Output
6
5
4
–V
S
4
5
NC
NC: No Connection
A87
1
2
3
Pin Orientation/Package Marking
PACKAGE/ORDERING INFORMATION
PACKAGE
DRAWING
NUMBER
(1)
182
SPECIFIED
TEMPERATURE
RANGE
–40°C to +85°C
PACKAGE
MARKING
OPA687U
ORDERING
NUMBER
(2)
OPA687U
OPA687U/2K5
OPA687N/250
OPA687N/3K
TRANSPORT
MEDIA
Rails
Tape and Reel
Tape and Reel
Tape and Reel
PRODUCT
OPA687U
PACKAGE
SO-8 Surface-Mount
"
OPA687N
"
6-Lead SOT23-6
"
332
"
–40°C to +85°C
"
A87
"
"
"
"
"
NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are
available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of “OPA687U/2K5” will get a single
2500-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.
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