NTE8212
Integrated Circuit
Schottky, 8–Bit Input/Output Port
Description:
The NTE8212 input/output port is an integrated circuit in a 24–Lead DIP type package and consists
of an 8–bit latch with three–state output buffers along with control and device selection logic. Also
included is a service request flip–flop for the control and generation of interrupts to the microprocessor.
Features:
D
Fully Parallel 8–Bit Data Register and Buffer
D
Service Request Flip–Flop for Interrupt Generation
D
Low Input Load Current: 0.25mA Max
D
Three State Outputs
D
Outputs Sink 15mA
D
3.65V Output High Voltge for Direct Interface to 8080A Processor
D
Asynchronous Register Clear
D
Replaces Buffers, Latches and Multiplexers in Microcomputer Systems
D
Reduces System Package Count
Absolute Maximum Ratings:
(T
A
= +25°C, Note 1 unless otherwise specified)
All Output or Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5V to +7V
All Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.0V to +5.5V
Output Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125mA
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0° to +70°C
Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65° to +150°C
Note 1. Stress above those listed under “Absolute Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
Electrical Characteristics:
(T
A
= 0° to +70°C, V
CC
= 5V
±5%
unless otherwise specified)
Parameter
DC Characteristics
Input Load Current
STB, DS
2
, CLR, DI
1
– DI
8
Inputs
MD Input
DS
1
Input
Input Leakage Current
STB, DS, CLR, DI
1
– DI
8
Inputs
MD Input
DS
1
Input
Input Forward Voltge Clamp
Input “Low” Voltage
Input “High” Voltage
Output “Low” Voltage
Output “High” Voltage
Short Circuit Output Current
Output Leakage Current, High Impedance
State (DO
0
– DO
8
)
Power Supply Current
AC Characteritics
Pulse Width
Data to Output Delay
Write Enable to Output Delay
data Setup Time
Data Hold Time
Reset to Output Delay
Set to Output Delay
Output Enable/Disable Time (Note 2)
Clear to Output Delay
t
pw
t
pd
t
we
t
set
t
h
t
r
t
s
t
e
/t
d
t
c
Input Pulse Amplitude = 2.5V,
Input Rise & Fall Times = 5ns,
Between 1V and 2V
Measurement made
at 1.5V with 15mA and 30pF
Test Load
30
–
–
15
20
–
–
–
–
–
–
–
–
–
–
–
–
–
–
30
40
–
–
40
30
45
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
|I
L1
|
|I
L2
|
|I
L3
|
|I
H1
|
|I
H2
|
|I
H3
|
V
C
V
IL
V
IH
V
OL
V
OH
I
O
5
I
O
I
CC
I
OL
= 15mA
I
OH
= –1mA
V
O
= 0V, V
CC
= 5V
V
O
= 0.45V/5.25V
I
C
= –5mA
V
R
= 5.25V
V
F
= 0.45V
–
–
–
–
–
–
–
–
2.0
–
3.65
–15
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–0.25
–0.75
–1.0
10
30
40
–1.0
0.85
–
0.48
–
–75
20
130
mA
mA
mA
µA
µA
µA
V
V
V
V
V
mA
µA
mA
Symbol
Test Conditions
Min
Typ
Max
Unit
Note 2. R
1
= 300Ω/10KΩ; R
2
= 600Ω/1KΩ
Capacitance:
(T
A
= +25°C, V
CC
= 5V, V
BIAS
= 2.5V, f = 1MHz, Note 3 unless otherwise specified)
Parameter
Input Capacitance
Input Capacitance
Output Capacitance
Symbol
C
IN
C
IN
C
OUT
DS
1
, MD
DS
2
, CLR, STB, DI
1
– DI
8
DO
1
– DO
8
Test Conditions
Min
–
–
–
Typ
–
–
–
Max
12
9
12
Unit
pF
pF
pF
Note 3. This parameter is periodically sampled and not 100% tested.
Functional Description:
Data Latch
The 8 flip–flops that compose the data latch are of a “D” type design. The output (Q) of the flip–flop
follows the data input (D) while the clock input (C) is high. Latching occurs when the clock (C) returns
low.
The data latch is cleared by an asynchronous reset input (CLR).
(NOTE: Clock (C) overrides Reset (CLR).)
Output Buffer
The outputs of the data latch (Q) are connected to three–state, non–inverting output buffers. These
buffers have a common control line (EN); enabling the buffer to transmit the data from the outputs of
the data latch (Q) or disabling the buffer, forcing the output into a high impedance state (three–state).
This high–impedance state allows the designer to connect the NTE8212 directly to the microproces-
sor bi–directional data bus.
Control Logic
The NTE8212 has four control inputs: DS
1
, DS
2
, MD and STB. These inputs are employed to control
device selection, data latching, output buffer state and the service request flip–flop.
DS
1
, DS
2
(Device Select)
These two inputs are employed for device selection. When DS
1
is low and DS
2
is high (DS
1
•
DS
2
)
the device is selected. In the selected state the output buffer is enabled and the service request flip–
flop (SR) is asynchronously set.
Service Request Flip–Flop (SR)
The (SR) flip–flop is employed to generate and control interrupts in microcomputer systems. It is asyn-
chronously set by the CLR input (active low). When the (SR) flip–flop is set it is in the non–interrupting
state.
The output (Q) of the (SR) flip–flop is connected to an inverting input of a “NOR” gate. The other input
of the “NOR” gate is non–inverting and is connected to the device selection logic (DS
1
•
DS
2
). The
output of the “NOR” gate (INT) is active low (interrupting state) for connection to active low input prior-
ity generating circuits.
MD (Mode)
This input is employed to control the state of the output buffer and to determine the source of the clock
(C) to the data latch.
When MD is in the output mode (high) the output buffers are enabled and the source of clock (C) to
the data latch is from the device selection logic (DS
1
•
DS
2
).
When MD is in the input mode (low) the output buffer state is determined by the device selection logic
(DS
1
•
DS
2
) and the source of clock (C) to the data latch is the STB (Strobe) input.
STB (Strobe)
STB is employed as the clock (C) to the data latch for the input mode (MD = 0) and to synchronously
reset the service request (SR) flip–flop.
Note that the SR flip–flop triggers on the negative edge of STB which overrides CLR.
Pin Connection Diagram
DS
1
1
MD
2
DI
1
3
DO
1
4
DI
2
5
DO
2
6
DI
3
7
DO
3
8
DI
4
9
DO
4
10
STB
11
GND
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
INT
DI
8
DO
8
DI
7
DO
7
DI
6
DO
6
DI
5
DO
5
CLR
DS
2
24
13
1
12
1.300 (33.02) Max
.520
(13.2)
.225
(5.73)
Max
.100 (2.54)
1.100 (27.94)
.126
(3.22)
Min
.600 (15.24)
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