74AUP1G79GW-G datasheet, PDF - EEWORLD Datasheet

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74AUP1G79GW-G: DescriptionFlip Flops 1.8V SINGLE D-TYPE; Categorysemiconductor logic; File Size371KB，24 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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74AUP1G79GW-G Overview

Flip Flops 1.8V SINGLE D-TYPE

74AUP1G79GW-G Parametric

Parameter Name	Attribute value
Product Category	Flip Flops
Manufacturer	NXP
RoHS	Details
Number of Circuits	1
Logic Family	AUP
Logic Type	CMOS
Polarity	Non-Inverting
Input Type	Single-Ended
Propagation Delay Time	17.3 ns
High Level Output Current	- 4 mA
Supply Voltage - Max	3.6 V
Minimum Operating Temperature	- 40 C
Maximum Operating Temperature	+ 125 C
Mounting Style	SMD/SMT
Package / Case	SOT-353
Packaging	Reel
Height	1 mm
Length	2.25 mm
Number of Input Lines	1
Number of Output Lines	1
Operating Supply Voltage	1.8 V, 2.5 V, 3.3 V
Factory Pack Quantity	3000
Supply Voltage - Min	0.8 V
Width	1.35 mm

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74AUP1G79

Low-power D-type flip-flop; positive-edge trigger

Rev. 6 — 28 June 2012

Product data sheet

1. General description

The 74AUP1G79 provides the single positive-edge triggered D-type flip-flop. Information

on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock

pulse. The D input must be stable one setup time prior to the LOW-to-HIGH clock

transition for predictable operation.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall

times across the entire V

range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire

range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using I

OFF

The I

OFF

circuitry disables the output, preventing the damaging backflow current through

the device when it is powered down.

2. Features and benefits



Wide supply voltage range from 0.8 V to 3.6 V



High noise immunity



Complies with JEDEC standards:



JESD8-12 (0.8 V to 1.3 V)



JESD8-11 (0.9 V to 1.65 V)



JESD8-7 (1.2 V to 1.95 V)



JESD8-5 (1.8 V to 2.7 V)



JESD8-B (2.7 V to 3.6 V)



ESD protection:



HBM JESD22-A114F Class 3A exceeds 5000 V



MM JESD22-A115-A exceeds 200 V



CDM JESD22-C101E exceeds 1000 V



Low static power consumption; I

= 0.9

A

(maximum)



Latch-up performance exceeds 100 mA per JESD 78 Class II



Inputs accept voltages up to 3.6 V



Low noise overshoot and undershoot < 10 % of V



OFF

circuitry provides partial power-down mode operation



Multiple package options



Specified from

40 C

to +85

C

and

40 C

to +125

C

74AUP1G79GW-G Related Products

	74AUP1G79GW-G	74AUP1G79GM-G
Description	Flip Flops 1.8V SINGLE D-TYPE	Flip Flops 1.8V SINGLE D-TYPE
Product Category	Flip Flops	Flip Flops
Manufacturer	NXP	NXP
RoHS	Details	Details
Number of Circuits	1	1
Logic Family	AUP	AUP
Logic Type	CMOS	CMOS
Polarity	Non-Inverting	Non-Inverting
Input Type	Single-Ended	Single-Ended
Propagation Delay Time	17.3 ns	17.3 ns
High Level Output Current	- 4 mA	- 4 mA
Supply Voltage - Max	3.6 V	3.6 V
Minimum Operating Temperature	- 40 C	- 40 C
Maximum Operating Temperature	+ 125 C	+ 125 C
Mounting Style	SMD/SMT	SMD/SMT
Package / Case	SOT-353	SOT-886
Packaging	Reel	Reel
Height	1 mm	0.46 mm
Length	2.25 mm	1.45 mm
Number of Input Lines	1	1
Number of Output Lines	1	1
Operating Supply Voltage	1.8 V, 2.5 V, 3.3 V	1.8 V, 2.5 V, 3.3 V
Factory Pack Quantity	3000	5000
Supply Voltage - Min	0.8 V	0.8 V
Width	1.35 mm	1 mm

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