AT29LV010A-25TC datasheet, PDF

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AT29LV010A-25TC: DescriptionFlash Memory 1M (128kx8) NRND; Categorystorage storage; File Size291KB，17 Pages; ManufacturerAtmel (Microchip)

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AT29LV010A-25TC Overview

Flash Memory 1M (128kx8) NRND

AT29LV010A-25TC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Atmel (Microchip)
Parts packaging code	TSOP1
package instruction	TSOP1, TSSOP32,.8,20
Contacts	32
Reach Compliance Code	compliant
ECCN code	EAR99
Maximum access time	250 ns
command user interface	NO
Data polling	YES
JESD-30 code	R-PDSO-G32
JESD-609 code	e0
length	18.4 mm
memory density	1048576 bit
Memory IC Type	FLASH
memory width	8
Humidity sensitivity level	3
Number of functions	1
Number of departments/size	1K
Number of terminals	32
word count	131072 words
character code	128000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128KX8
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP1
Encapsulate equivalent code	TSSOP32,.8,20
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	240
power supply	3.3 V
Programming voltage	3 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Department size	128
Maximum standby current	0.00004 A
Maximum slew rate	0.015 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
switch bit	YES
type	NOR TYPE
width	8 mm
Maximum write cycle time (tWC)	20 ms

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Features

•

Single Supply Voltage, Range 3V to 3.6V

3-volt Only Read and Write Operation

Software Protected Programming

Fast Read Access Time – 120 ns

Low Power Dissipation

– 15 mA Active Current

– 40 µA CMOS Standby Current

Sector Program Operation

– Single Cycle Reprogram (Erase and Program)

– 1024 Sectors (128 Bytes/Sector)

– Internal Address and Data Latches for 128 Bytes

Two 8K Bytes Boot Blocks with Lockout

Fast Sector Program Cycle Time – 20 ms

Internal Program Control and Timer

DATA Polling for End of Program Detection

Typical Endurance > 10,000 Cycles

CMOS and TTL Compatible Inputs and Outputs

Commercial and Industrial Temperature Ranges

•

1-megabit

(128K x 8)

3-volt Only

Flash Memory

AT29LV010A

Not Recommended

for New Designs.

Use AT29BV010A.

1. Description

The AT29LV010A is a 3-volt only in-system Flash programmable and erasable read

only memory (Flash). Its 1 megabit of memory is organized as 131,072 bytes by 8 bits.

Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers

access times to 120 ns with power dissipation of just 54 mW over the commercial tem-

perature range. When the device is deselected, the CMOS standby current is less

than 40 µA. The device endurance is such that any sector can typically be written to in

excess of 10,000 times.

To allow for simple in-system reprogrammability, the AT29LV010A does not require

high input voltages for programming. Three-volt-only commands determine the opera-

tion of the device. Reading data out of the device is similar to reading from an

EPROM. Reprogramming the AT29LV010A is performed on a sector basis; 128 bytes

of data are loaded into the device and then simultaneously programmed.

During a reprogram cycle, the address locations and 128 bytes of data are captured at

microprocessor speed and internally latched, freeing the address and data bus for

other operations. Following the initiation of a program cycle, the device will automati-

cally erase the sector and then program the latched data using an internal control

timer. The end of a program cycle can be detected by DATA polling of I/O7. Once the

end of a program cycle has been detected, a new access for a read or program can

begin.

0520F–FLASH–9/08

AT29LV010A

3. Block Diagram

4. Device Operation

4.1

Read

The AT29LV010A is accessed like an EPROM. When CE and OE are low and WE is high, the

data stored at the memory location determined by the address pins is asserted on the outputs.

The outputs are put in the high impedance state whenever CE or OE is high. This dual-line con-

trol gives designers flexibility in preventing bus contention.

4.2

Software Data Protection Programming

The AT29LV010A has 1024 individual sectors, each 128 bytes. Using the software data protec-

tion feature, byte loads are used to enter the 128 bytes of a sector to be programmed. The

AT29LV010A can only be programmed or reprogrammed using the software data protection fea-

ture. The device is programmed on a sector basis. If a byte of data within the sector is to be

changed, data for the entire 128-byte sector must be loaded into the device. The data in any

byte that is not loaded during the programming of its sector will be indeterminate. The

AT29LV010A automatically does a sector erase prior to loading the data into the sector. An

erase command is not required.

Software data protection protects the device from inadvertent programming. A series of three

program commands to specific addresses with specific data must be presented to the device

before programming may occur. The same three program commands must begin each program

operation. All software program commands must obey the sector program timing specifications.

Power transitions will not reset the software data protection feature; however, the software fea-

ture will guard against inadvertent program cycles during power transitions.

Any attempt to write to the device without the 3-byte command sequence will start the internal

write timers. No data will be written to the device; however, for the duration of t

, a read opera-

tion will effectively be a polling operation.

After the software data protection’s 3-byte command code is given, a byte load is performed by

applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The

address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by

the first rising edge of CE or WE.

The 128 bytes of data must be loaded into each sector. Any byte that is not loaded during the

programming of its sector will be erased to read FFh. Once the bytes of a sector are loaded into

0520F–FLASH–9/08

the device, they are simultaneously programmed during the internal programming period. After

the first data byte has been loaded into the device, successive bytes are entered in the same

manner. Each new byte to be programmed must have its high to low transition on WE (or CE)

within 150 µs of the low-to-high transition of WE (or CE) of the preceding byte. If a high to low

transition is not detected within 150 µs of the last low-to-high transition, the load period will end

and the internal programming period will start. A7 to A16 specify the sector address. The sector

address must be valid during each high to low transition of WE (or CE). A0 to A6 specify the byte

address within the sector. The bytes may be loaded in any order; sequential loading is not

required. Once a programming operation has been initiated, and for the duration of t

, a read

operation will effectively be a polling operation.

4.3

Hardware Data Protection

Hardware features protect against inadvertent programs to the AT29LV010A in the following

ways: (a) V

sense – if V

is below 1.8V (typical), the program function is inhibited; (b) V

power on delay – once V

has reached the V

sense level, the device will automatically time

out 10 ms (typical) before programming; (c) Program inhibit – holding any one of OE low, CE

high or WE high inhibits program cycles; and (d) Noise filter – pulses of less than 15 ns (typical)

on the WE or CE inputs will not initiate a program cycle.

4.4

Input Levels

While operating with a 3.3V

0.3V power supply, the address inputs and control inputs (OE, CE

and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the device.

The I/O lines can be driven from 0 to V

+ 0.6V.

4.5

Product Identification

The product identification mode identifies the device and manufacturer as Atmel. It may be

accessed by hardware or software operation. The hardware operation mode can be used by an

external programmer to identify the correct programming algorithm for the Atmel product.

In addition, users may wish to use the software product identification mode to identify the part

(i.e. using the device code), and have the system software use the appropriate sector size for

program operations. In this manner, the user can have a common board design for 256K to

4-megabit densities and, with each density’s sector size in a memory map, have the system soft-

ware apply the appropriate sector size.

For details, see Operating Modes (for hardware operation) or Software Product Identification.

The manufacturer and device code is the same for both modes.

4.6

DATA Polling

The AT29LV010A features DATA polling to indicate the end of a program cycle. During a pro-

gram cycle an attempted read of the last byte loaded will result in the complement of the loaded

data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and

the next cycle may begin. DATA polling may begin at any time during the program cycle.

4.7

Toggle Bit

In addition to DATA polling the AT29LV010A provides another method for determining the end

of a program or erase cycle. During a program or erase operation, successive attempts to read

data from the device will result in I/O6 toggling between one and zero. Once the program cycle

has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may

begin at any time during a program cycle.

AT29LV010A

0520F–FLASH–9/08

AT29LV010A

4.8

Optional Chip Erase Mode

The entire device can be erased by using a 6-byte software code. Please see Software Chip

Erase application note for details.

4.9

Boot Block Programming Lockout

The AT29LV010A has two designated memory blocks that have a programming lockout feature.

This feature prevents programming of data in the designated block once the feature has been

enabled. Each of these blocks consists of 8K bytes; the programming lockout feature can be set

independently for either block. While the lockout feature does not have to be activated, it can be

activated for either or both blocks.

These two 8K memory sections are referred to as

boot blocks.

Secure code which will bring up a

system can be contained in a boot block. The AT29LV010A blocks are located in the first 8K

bytes of memory and the last 8K bytes of memory. The boot block programming lockout feature

can therefore support systems that boot from the lower addresses of memory or the higher

addresses. Once the programming lockout feature has been activated, the data in that block can

no longer be erased or programmed; data in other memory locations can still be changed

through the regular programming methods. To activate the lockout feature, a series of seven

program commands to specific addresses with specific data must be performed. Please see

Boot Block Lockout Feature Enable Algorithm.

If the boot block lockout feature has been activated on either block, the chip erase function will

be disabled.

4.9.1

Boot Block Lockout Detection

A software method is available to determine whether programming of either boot block section is

locked out. See Software Product Identification Entry and Exit sections. When the device is in

the software product identification mode, a read from location 00002H will show if programming

the lower address boot block is locked out while reading location 1FFF2H will do so for the upper

boot block. If the data is FE, the corresponding block can be programmed; if the data is FF, the

program lockout feature has been activated and the corresponding block cannot be pro-

grammed. The software product identification exit mode should be used to return to standard

operation.

5. Absolute Maximum Ratings*

Temperature Under Bias............................... -55° C to +125° C

Storage Temperature .................................... -65° C to +150° C

All Input Voltages (including NC Pins)

with Respect to Ground ...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground .............................-0.6V to V

+ 0.6V

Voltage on A9 (including NC Pins)

with Respect to Ground ...................................-0.6V to +13.5V

*NOTICE:

Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect device

reliability.

0520F–FLASH–9/08

AT29LV010A-25TC Related Products

	AT29LV010A-25TC	AT29LV010A-12JI	AT29LV010A-12JC	BLU1206P-1211-TT5W
Description	Flash Memory 1M (128kx8) NRND	Flash Memory 1M (128K X 8) 3.3V- 120NS IND TEMP	Flash Memory 1M (128K X 8) 3.3V- 120NS COM TEMP	Res,SMT,Thin Film,1.21K Ohms,150WV,.01% +/-Tol,5ppm TC,1206 Case
Is it Rohs certified?	incompatible	incompatible	incompatible	conform to
Reach Compliance Code	compliant	compliant	compliant	compliant
ECCN code	EAR99	EAR99	EAR99	EAR99
JESD-609 code	e0	e0	e0	e3
Number of terminals	32	32	32	2
Maximum operating temperature	70 °C	85 °C	70 °C	155 °C
Package form	SMALL OUTLINE, THIN PROFILE	CHIP CARRIER	CHIP CARRIER	SMT
technology	CMOS	CMOS	CMOS	THIN FILM
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Matte Tin (Sn) - with Nickel (Ni) barrier
Maker	Atmel (Microchip)	Atmel (Microchip)	Atmel (Microchip)	-
Parts packaging code	TSOP1	QFJ	QFJ	-
package instruction	TSOP1, TSSOP32,.8,20	QCCJ, LDCC32,.5X.6	QCCJ, LDCC32,.5X.6	-
Contacts	32	32	32	-
Maximum access time	250 ns	120 ns	120 ns	-
command user interface	NO	NO	NO	-
Data polling	YES	YES	YES	-
JESD-30 code	R-PDSO-G32	R-PQCC-J32	R-PQCC-J32	-
length	18.4 mm	13.97 mm	13.97 mm	-
memory density	1048576 bit	1048576 bit	1048576 bit	-
Memory IC Type	FLASH	FLASH	FLASH	-
memory width	8	8	8	-
Humidity sensitivity level	3	2	2	-
Number of functions	1	1	1	-
Number of departments/size	1K	1K	1K	-
word count	131072 words	131072 words	131072 words	-
character code	128000	128000	128000	-
Operating mode	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	-
organize	128KX8	128KX8	128KX8	-
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-
encapsulated code	TSOP1	QCCJ	QCCJ	-
Encapsulate equivalent code	TSSOP32,.8,20	LDCC32,.5X.6	LDCC32,.5X.6	-
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	-
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	-
Peak Reflow Temperature (Celsius)	240	225	225	-
power supply	3.3 V	3.3 V	3.3 V	-
Programming voltage	3 V	3 V	3 V	-
Certification status	Not Qualified	Not Qualified	Not Qualified	-
Maximum seat height	1.2 mm	3.56 mm	3.56 mm	-
Department size	128	128	128	-
Maximum standby current	0.00004 A	0.00005 A	0.00004 A	-
Maximum slew rate	0.015 mA	0.015 mA	0.015 mA	-
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	-
Minimum supply voltage (Vsup)	3 V	3 V	3 V	-
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	-
surface mount	YES	YES	YES	-
Temperature level	COMMERCIAL	INDUSTRIAL	COMMERCIAL	-
Terminal form	GULL WING	J BEND	J BEND	-
Terminal pitch	0.5 mm	1.27 mm	1.27 mm	-
Terminal location	DUAL	QUAD	QUAD	-
Maximum time at peak reflow temperature	30	30	30	-
switch bit	YES	YES	YES	-
type	NOR TYPE	NOR TYPE	NOR TYPE	-
width	8 mm	11.43 mm	11.43 mm	-
Maximum write cycle time (tWC)	20 ms	20 ms	20 ms	-

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