SY89218U
Precision 1:15 LVDS Fanout Buffer with 2:1
MUX and Four ÷1/÷2/÷4 Clock Divider Output
Banks
General Description
The SY89218U is a 2.5V precision, high-speed,
integrated clock divider and LVDS fanout buffer capable
of handling clocks up to 1.5GHz. Optimized for
communications applications, the four independently
controlled output banks are phase-matched and can be
configured for pass through (÷1), ÷2 or ÷4 divider ratios.
The differential input includes Micrel’s unique, 3-pin
input termination architecture that allows the user to
interface to any differential signal (AC- or DC-coupled)
as small as 100mV (200mV
PP
) without any level shifting
or termination resistor networks in the signal path. The
low-skew, low-jitter outputs are LVDS compatible with
extremely fast rise/fall times guaranteed to be less than
200ps.
The /MR (master reset) input asynchronously resets the
outputs. A four-clock delay after de-asserting /MR allows
the counters to synchronize and start the outputs from
the same state without any runt pulse.
The SY89218U is part of Micrel’s Precision Edge
®
product family. All support documentation can be found
at Micrel's web site at:
www.micrel.com.
Features
•
Low-skew LVDS output banks with independently
programmable ÷1, ÷2 and ÷4 divider options
•
Four output banks, 15 total outputs
•
Guaranteed AC performance over temperature and
voltage:
– Accepts a clock frequency up to 1.5GHz
– <1600ps IN-to-OUT propagation delay
– <200ps rise/fall time
– <35ps within bank skew
•
Fail Safe Input
– Prevents outputs from oscillating
•
Ultra-low jitter design:
– <1ps
RMS
random jitter
– <10ps
PP
total jitter (clock)
•
Patent-pending input termination and VT pin accepts
DC- and AC-coupled inputs (CML, PECL, LVDS)
•
LVDS-compatible outputs
•
CMOS/TTL-compatible output enable (EN) and
divider select control
•
2.5V ±5% power supply
•
–40°C to +85°C temperature range
•
Available in 64-pin TQFP
Applications
•
All SONET/SDH applications
•
All Fibre Channel applications
•
All Gigabit Ethernet applications
Markets
•
•
•
•
LAN/WAN routers/switches
Storage
ATE
Test and measurement
United States Patent No. RE44,134
Precision Edge is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
August 2007
M9999-082407-C
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY89218U
Functional Block Diagram
August 2007
2
M9999-082407-C
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY89218U
Ordering Information
(1)
Part Number
SY89218UHY
SY89218UHYTR
(2)
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A
= 25°C, DC Electricals only.
2. Tape and Reel.
Package
Type
T64-1
T64-1
Operating
Range
Industrial
Industrial
Package Marking
SY89218UHY with
Pb-Free bar-line indicator
SY89218UHY with
Pb-Free bar-line indicator
Lead
Finish
Pb-Free
Matte-Sn
Pb-Free
Matte-Sn
Pin Configuration
64-Pin EPAD-TQFP (T64-1)
August 2007
3
M9999-082407-C
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY89218U
Pin Description
Pin Number
1, 2
3, 4
15, 16
17, 18
5, 8,
11, 14
Pin Name
FSELA1, FSELA0
FSELB1, FSELB0
FSELC1, FSELC0
FSELD1, FSELD0
IN0, /IN0
IN1, /IN1
Pin Function
Single-Ended Inputs: These TTL/CMOS inputs select the divide ratio for each of the
four banks of outputs. Note that each of these inputs is internally connected to a 25kΩ
pull-up resistor and will default to a logic HIGH state if left open. The input-switching
threshold is V
CC
/2.
Differential Inputs: These input pairs are the differential signal inputs to the device.
These inputs accept AC- or DC-coupled signals as small as 100mV. The input pairs
internally terminate to a VT pin through 50Ω. Note that these inputs will default to an
indeterminate state if left open. Please refer to the “Input Interface Applications”
section for more details.
Input Termination Center-Tap: Each side of a differential input pair terminates to a VT
pin. The VT pin provides a center-tap to a termination network for maximum interface
flexibility. See “ Input Interface Applications” section for more details.
Reference Voltage: These outputs bias to V
CC
–1.2V. They are used for AC-coupling
inputs IN and /IN. Connect VREF-AC directly to the corresponding VT pin. Bypass with
0.01µF low ESR capacitor to VCC. Due to limited drive capability, the VREF-AC pin is
only intended to drive its respective VT pin. Maximum sink/source current is ±1.5mA.
Please refer to the “Input Interface Applications” section for more details.
Single-Ended Input: This TTL/CMOS-compatible master reset function asynchronously
sets the true outputs LOW, complimentary outputs HIGH, and holds them in that state
as long as /MR remains LOW. This input is internally connected to a 25kΩ pull-up
resistor and will default to logic HIGH state if left open. The input-switching threshold is
V
CC
/2.
Single-Ended Input: This single-ended TTL/CMOS-compatible input selects the inputs
to the multiplexer. Note that this input is internally connected to a 25kΩ pull-up resistor
and will default to logic HIGH state if left open. The input-switching threshold is V
CC
/2.
Positive Power Supply. Bypass with a 0.1µF||0.01µF low ESR capacitor as close to
V
CC
pin as possible.
6, 12
VT0, VT1
7,
13
VREF-AC0,
VREF-AC1
9
/MR
10
CLK_SEL
20, 25, 30, 33,
40
41, 48, 50, 55,
62
21, 22
23, 24
26, 27
28, 29
31
34, 35,
36, 37
38, 39,
42, 43
44, 45,
46, 47
51, 52
53, 54
56, 57
58, 59
60, 61
VCC
/QC0, QC0
/QC1, QC1
/QC2, QC2
/QC3, QC3
NC
/QD0, QD0
/QD1, QD1
/QD2, QD2
/QD3, QD3
/QD4, QD4
/QD5, QD5
/QA0, QA0
/QA1, QA1
/QB0, QB0
/QB1, QB1
/QB2, QB2
Bank C LVDS differential output pairs controlled by FSELC1 and FSELC0. Refer to
“Function Table” for details. Unused output pairs should be terminated with 100Ω
across the differential pair
No connect.
Bank D LVDS differential output pairs controlled by FSELD1 and FSELD0. Refer to
“Function Table” for details. Unused output pairs should be terminated with 100Ω
across the differential pair
Bank A LVDS differential output pairs controlled by FSELA1 and FSELA0. Refer to
“Function Table” for details. Unused output pairs should be terminated with 100Ω
across the differential pair
Bank B LVDS differential output pairs controlled by FSELB1 and FSELB0. Refer to
“Function Table” for details. Unused output pairs should be terminated with 100Ω
across the differential pair
August 2007
4
M9999-082407-C
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY89218U
Pin Description
(continued)
Pin Number
64
Pin Name
EN
Pin Function
Single-Ended Input: This TTL/CMOS input disables and enables the outputs. It is
internally connected to a 25kΩ pull-up resistor and will default to logic HIGH state if left
open. When disabled, true outputs go LOW and complementary outputs switch to HIGH.
The input switching threshold is V
CC
/2. For the input enable and disable functional
description, refer to Figures 2d and 2e.
Ground and exposed pad must be connected to the same GND plane on the board.
19, 32, 49, 63
GND,
Exposed Pad
Function Table
/MR
(1)
1
1
1
1
1
1
1
0
Notes:
1.
2.
3.
4.
/MR asynchronously forces Q to LOW (/Q to HIGH).
EN forces Q LOW between 2 and 6 input clock cycles after the falling edge of EN. Refer to “Timing Diagram” section.
EN synchronously enables Q between two and six input clock cycles after the rising edge of EN. Refer to “Timing Diagram” section.
FSEL valid for each of the banks A, B, C, and D. Banks can be programmed independent of each other.
EN
(2, 3)
1
1
1
1
1
1
0
X
CLK_SEL
0
1
0
1
0
1
X
X
FSELx0
(4)
0
0
1
1
X
X
X
X
FSELx1
(4)
0
0
0
0
1
1
X
X
Q
IN0÷1
IN1÷1
IN0÷2
IN1÷2
IN0÷4
IN1÷4
0
0
August 2007
5
M9999-082407-C
hbwhelp@micrel.com
or (408) 955-1690
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