GAL20VP8
High-Speed E
2
CMOS PLD
Generic Array Logic™
Features
• HIGH DRIVE E
2
CMOS
®
GAL
®
DEVICE
— TTL Compatible 64 mA Output Drive
— 15 ns Maximum Propagation Delay
— Fmax = 80 MHz
— 10 ns Maximum from Clock Input to Data Output
— UltraMOS
®
Advanced CMOS Technology
• ENHANCED INPUT AND OUTPUT FEATURES
— Schmitt Trigger Inputs
— Programmable Open-Drain or Totem-Pole Outputs
— Active Pull-Ups on All Inputs and I/O pins
• E
2
CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• EIGHT OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
— Architecturally Compatible with Standard GAL20V8
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— 100% Functional Testability
• APPLICATIONS INCLUDE:
— Ideal for Bus Control & Bus Arbitration Logic
— Bus Address Decode Logic
— Memory Address, Data and Control Circuits
— DMA Control
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
I
8
I
OLMC
I/O/Q
Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
Functional Block Diagram
I/CLK
I
I
IMUX
CLK
8
OLMC
I/O/Q
PROGRAMMABLE
AND-ARRAY
(64 X 40)
8
OLMC
I/O/Q
I
8
OLMC
I/O/Q
I
8
OLMC
I/O/Q
I
8
OLMC
I/O/Q
I
8
I
8
OLMC
OE
OLMC
I/O/Q
I/O/Q
I
I
I
IMUX
I/OE
Description
The GAL20VP8, with 64 mA drive capability and 15 ns maximum
propagation delay time is ideal for Bus and Memory control appli-
cations.
The GAL20VP8 is manufactured using Lattice
Semiconductor's advanced E
2
CMOS process which combines
CMOS with Electrically Erasable (E
2
) floating gate technology. High
speed erase times (<100ms) allow the devices to be reprogrammed
quickly and efficiently.
System bus and memory interfaces require control logic before
driving the bus or memory interface signals. The GAL20VP8
combines the familiar GAL20V8 architecture with bus drivers as
its outputs. The generic architecture provides maximum design flex-
ibility by allowing the Output Logic Macrocell (OLMC) to be con-
figured by the user. The 64mA output drive eliminates the need for
additional devices to provide bus-driving capability.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result,
Lattice Semiconductor delivers 100% field programmability and
functionality of all GAL products. In addition, 100 erase/write cycles
and data retention in excess of 20 years are specified.
Pin Configuration
PLCC
I/CLK
I/CLK
I/O/Q
NC
DIP
1
24
I
I
I/O/Q
I
I
25
I/O/Q
I/O/Q
I
I
28
4
I
I
Vcc
NC
I
I
I
11
12
9
7
5
I
2
I
26
I
I
Vcc
I
I
I
I
I
I/OE
12
6
GAL
20VP8
18
I/O/Q
I/O/Q
I/O/Q
GND
I/O/Q
I/O/Q
I/O/Q
I/O/Q
13
I
GAL20VP8
Top View
14
16
23
I/O/Q
NC
21
GND
I/O/Q
19
18
I/O/Q
I/OE
I/O/Q
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
I/O/Q
I
I
NC
I
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
December 1997
20vp8_03
1
Specifications
GAL20VP8
Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
GAL20VP8 Ordering Information
Commercial Grade Specifications
Tpd (ns)
15
Tsu (ns)
8
Tco (ns)
10
Icc (mA)
115
115
Ordering #
GAL20VP8B-15LP
GAL20VP8B-15LJ
GAL20VP8B-25LP
GAL20VP8B-25LJ
Package
24-Pin Plastic DIP
28-Lead PLCC
24-Pin Plastic DIP
28-Lead PLCC
25
10
15
115
115
Part Number Description
XXXXXXXX
_
XX
X
X X
GAL20VP8B
Device Name
Grade
Blank = Commercial
Speed (ns)
L = Low Power
Power
Package
P = Plastic DIP
J = PLCC
2
Specifications
GAL20VP8
Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
Output Logic Macrocell (OLMC)
The following discussion pertains to configuring the output logic
macrocell. It should be noted that actual implementation is accom-
plished by development software/hardware and is completely trans-
parent to the user.
There are three global OLMC configuration modes possible:
simple, complex,
and
registered.
Details of each of these modes
is illustrated in the following pages. Two global bits, SYN and AC0,
control the mode configuration for all macrocells. The XOR bit of
each macrocell controls the polarity of the output in any of the three
modes, while the AC1 and AC2 bit of each of the macrocells controls
the input/output and totem-pole/open-drain configuration. These
two global and 24 individual architecture bits define all possible con-
figurations in a GAL20VP8. The information given on these archi-
tecture bits is only to give a better understanding of the device.
Compiler software will transparently set these architecture bits from
the pin definitions, so the user should not need to directly manipulate
these architecture bits.
Compiler Support for OLMC
Software compilers support the three different global OLMC modes
as different device types. Most compilers also have the ability to
automatically select the device type, generally based on the register
usage and output enable (OE) usage. Register usage on the device
forces the software to choose the registered mode. All combina-
torial outputs with OE controlled by the product term will force the
software to choose the complex mode. The software will choose
the simple mode only when all outputs are dedicated combinatorial
without OE control. For further details, refer to the compiler soft-
ware manuals.
When using compiler software to configure the device, the user
must pay special attention to the following restrictions in each mode.
In
registered mode
pin 1(2) and pin 12(14) are permanently con-
figured as clock and output enable, respectively. These pins cannot
be configured as dedicated inputs in the registered mode.
In
complex mode
pin 1(2) and pin 12(14) become dedicated in-
puts and use the feedback paths of pin 22(26) and pin 14(17) re-
spectively. Because of this feedback path usage, pin 22(26) and
pin 14(17) do not have the feedback option in this mode.
In
simple mode
all feedback paths of the output pins are routed
via the adjacent pins. In doing so, the two inner most pins (pins
17(20) and 19(23)) will not have the feedback option as these pins
are always configured as dedicated combinatorial output.
In addition to the architecture configurations, the logic compiler
software also supports configuration of either totem-pole or open-
drain outputs. The actual architecture bit configuration, again, is
transparent to the user with the default configuration being the
standard totem-pole output.
3
Specifications
GAL20VP8
Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
Registered Mode
In the Registered mode, macrocells are configured as dedicated
registered outputs or as I/O functions.
All registered macrocells share common clock and output enable
control pins. Any macrocell can be configured as registered or I/
O. Up to eight registers or up to eight I/Os are possible in this mode.
Dedicated input or output functions can be implemented as sub-
sets of the I/O function.
Registered outputs have eight product terms per output. I/Os have
seven product terms per output.
The JEDEC fuse numbers, including the User Electronic Signature
(UES) fuses and the Product Term Disable (PTD) fuses, are shown
on the logic diagram on the following page.
CLK
Registered Configuration for Registered Mode
- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this output configuration.
- AC2=1 defines totem pole output.
- AC2=0 defines open-drain output.
- Pin 1(2) controls common CLK for the registered
outputs.
- Pin 12(14) controls common
OE
for the registered
outputs.
- Pin 1(2) & Pin 12(14) are permanently configured as
CLK &
OE
for registered output configuration.
D
Q
Q
XOR
OE
Combinatorial Configuration for Registered Mode
- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1 defines this output configuration.
- AC2=1 defines totem pole output.
- AC2=0 defines open-drain output.
- Pin 1(2) & Pin 12(14) are permanently configured as
CLK &
OE.
for registered output configuration.
XOR
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
4
Specifications
GAL20VP8
Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
Registered Mode Logic Diagram
DIP (PLCC) Package Pinouts
1(2)
24(28)
0
4
8
12
16
20
24
28
32
36
PTD
2640
23(27)
0000
OLMC
XOR-2560
AC1-2632
AC2-2706
22(26)
0280
2(3)
0320
OLMC
XOR-2561
AC1-2633
AC2-2707
21(25)
0600
3(4)
0640
OLMC
XOR-2562
AC1-2634
AC2-2708
20(24)
0920
4(5)
0960
OLMC
XOR-2563
AC1-2635
AC2-2709
19(23)
1240
5(6)
1280
OLMC
XOR-2564
AC1-2636
AC2-2710
17(20)
1560
7(9)
1600
OLMC
XOR-2565
AC1-2637
AC2-2711
16(19)
1880
8(10)
1920
OLMC
XOR-2566
AC1-2638
AC2-2712
15(18)
2200
9(11)
2240
OLMC
XOR-2567
AC1-2639
AC2-2713
14(17)
2520
10(12)
11(13)
13(16)
OE
2703
12(14)
64-USER ELECTRONIC SIGNATURE FUSES
2568, 2569, ....
.... 2630, 2631
Byte7 Byte6 ....
.... Byte1 Byte0
MSB
LSB
SYN-2704
AC0-2705
5
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