ADF4355-3BCPZ-RL7 datasheet, PDF

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ADF4355-3BCPZ-RL7: DescriptionPhase Locked Loops - PLL 6.6GHz PLL with integrated VCO; CategoryTopical application Wireless rf/communication; File Size877KB，34 Pages; ManufacturerADI; Websitehttps://www.analog.com

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ADF4355-3BCPZ-RL7 Overview

Phase Locked Loops - PLL 6.6GHz PLL with integrated VCO

ADF4355-3BCPZ-RL7 Parametric

Parameter Name	Attribute value
Product Category	Phase Locked Loops - PLL
Manufacturer	ADI
RoHS	Details
Packaging	Reel
Factory Pack Quantity	1500

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Data Sheet

FEATURES

RF output frequency range: 51.5625 MHz to 6600 MHz

Fractional-N synthesizer and integer-N synthesizer

High resolution 38-bit modulus

Low phase noise, voltage controlled oscillator (VCO)

Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output

All power supplies: 3.3 V

Logic compatibility: 1.8 V

Programmable dual modulus prescaler of 4/5 or 8/9

Programmable output power level

RF output mute function

3-wire serial interface

Analog and digital lock detect

Microwave Wideband Synthesizer

with Integrated VCO

ADF4355-3

GENERAL DESCRIPTION

The

ADF4355-3

allows the implementation of fractional-N or

integer-N phase-locked loop (PLL) frequency synthesizers when

used with an external loop filter and an external reference

frequency. A series of frequency dividers at the output provide

operation from 51.5625 MHz to 6600 MHz.

The

ADF4355-3

has an integrated VCO with a fundamental

output frequency ranging from 3300 MHz to 6600 MHz. In

addition, the VCO frequency is connected to divide by 1, 2, 4, 8,

16, 32, or 64 circuits that allow the user to generate RF output

frequencies as low as 51.5625 MHz. For applications that require

isolation, the RF output stage can be muted. The mute function

is both pin- and software-controllable.

Control of all on-chip registers is through a simple 3-wire interface.

The

ADF4355-3

operates with analog, digital, charge pump, and

VCO power supplies ranging from 3.1515 V to 3.4485 V. The

ADF4355-3

also contains hardware and software power-down

modes.

APPLICATIONS

Wireless infrastructure (W-CDMA, TD-SCDMA,

WiMAX, GSM, PCS, DCS, DECT)

Point to point/point to multipoint microwave links

Satellites/VSATs

Test equipment/instrumentation

Clock generation

FUNCTIONAL BLOCK DIAGRAM

SET

VCO

REF

×2

DOUBLER

10-BIT R

COUNTER

÷2

DIVIDER

MULTIPLEXER

LOCK

DETECT

MUXOUT

REG

CLK

DATA

DATA REGISTER

FUNCTION

LATCH

PHASE

COMPARATOR

CHARGE

PUMP

OUT

REF

INTEGER

REG

FRACTION

REG

MODULUS

REG

VCO

CORE

TUNE

BIAS

REGVCO

1/2/4/8

16/32/64

OUTPUT

STAGE

OUT

A+

OUT

A–

PDB

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

N COUNTER

OUTPUT

STAGE

MULTIPLEXER

OUT

B–

OUT

B+

GND

GNDRF

GND

GNDVCO

Figure 1.

Rev. B

Document Feedback

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

13345-001

ADF4355-3

ADF4355-3

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings ............................................................ 6

Transistor Count ........................................................................... 6

ESD Caution .................................................................................. 6

Pin Configuration and Function Descriptions ............................. 7

Typical Performance Characteristics ............................................. 9

Theory of Operation ...................................................................... 12

Reference Input Section ............................................................. 12

RF N Divider ............................................................................... 12

Phase Frequency Detector (PFD) and Charge Pump ............ 13

MUXOUT and Lock Detect ...................................................... 13

Input Shift Registers ................................................................... 13

Program Modes .......................................................................... 14

VCO.............................................................................................. 14

Output Stage ................................................................................ 14

Loop Filter ................................................................................... 14

Data Sheet

Frequency Update Sequence ..................................................... 30

RF Synthesizer—A Worked Example ...................................... 30

Reference Doubler and Reference Divider ............................. 30

Spurious Optimization and Fast Lock ..................................... 31

Optimizing Jitter ......................................................................... 31

Spur Mechanisms ....................................................................... 31

Lock Time.................................................................................... 31

Applications Information .............................................................. 32

Direct Conversion Modulator .................................................. 32

Power Supplies ............................................................................ 33

Printed Circuit Board (PCB) Design Guidelines for a Chip-

Scale Package .............................................................................. 33

Output Matching ........................................................................ 33

Outline Dimensions ....................................................................... 34

Ordering Guide .......................................................................... 34

REVISION HISTORY

8/2017—Rev. A to Rev. B

Changes to Frequency Update Sequence .................................... 30

Updated Outline Dimensions ....................................................... 34

Changes to Ordering Guide .......................................................... 34

1/2016—Rev. 0 to Rev. A

Change to Integrated RMS Jitter Parameter, Unit Column,

Table 1 ................................................................................................ 4

Changes to Reference Input Section ............................................ 12

Changes to Table 6 .......................................................................... 15

Changes to Figure 25...................................................................... 17

Changes to Reference Mode Section ........................................... 23

Changes to Negative Bleed Section .............................................. 24

Changes to Charge Pump Bleed Current Section ...................... 25

Changes to Figure 34, Figure 35, and Register 8 Section .......... 27

Changes to Figure 37 and Register 11 Section ........................... 28

7/2015—Revision 0: Initial Version

Rev. B | Page 2 of 34

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	ADF4355-3BCPZ-RL7	EV-ADF4355-3SD1Z
Description	Phase Locked Loops - PLL 6.6GHz PLL with integrated VCO	EVAL BOARD ADF4355

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