Changes to Reference Input Section ............................................ 12
Changes to Table 6 .......................................................................... 15
Changes to Figure 25...................................................................... 17
Changes to Reference Mode Section ........................................... 23
Changes to Negative Bleed Section .............................................. 24
Changes to Charge Pump Bleed Current Section ...................... 25
Changes to Figure 34, Figure 35, and Register 8 Section .......... 27
Changes to Figure 37 and Register 11 Section ........................... 28
7/2015—Revision 0: Initial Version
Rev. B | Page 2 of 34
Data Sheet
SPECIFICATIONS
ADF4355-3
AV
DD
= DV
DD
= V
RF
= V
P
= V
VCO
= V
REGVCO
= 3.3 V ± 4.5%, A
GND
= CP
GND
= A
GNDVCO
= SD
GND
= A
GNDRF
= 0 V, R
SET
= 5.1 kΩ, dBm referred
to 50 Ω, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter
REF
IN
A/REF
IN
B CHARACTERISTICS
Input Frequency
Single-Ended Mode
Differential Mode
Doubler Enabled
Input Sensitivity
Single-Ended Mode
Differential Mode
Input Capacitance
Single-Ended Mode
Differential Mode
Input Current
Phase Detector Frequency
CHARGE PUMP (CP)
Charge Pump Current, Sink/Source
High
Low
R
SET
Range
Current Matching
I
CP
vs. V
CP1
I
CP
vs. Temperature
LOGIC INPUTS
Input Voltage
High
Low
Input Current
Input Capacitance
LOGIC OUTPUTS
Output Voltage
High
Low
Output High Current
POWER SUPPLIES
Analog Power
Digital Power, RF Supply, Charge Pump,
and VCO Supply Voltage
Charge Pump Supply Current
DI
DD
+ AI
DD 3
Output Dividers
VCO Supply Current
RF
OUT
A±/RF
OUT
B± Supply Current
Low Power Sleep Mode
Symbol
REF
IN
10
10
250
600
100
AV
DD
1.8
MHz
MHz
MHz
V p-p
V p-p
Min
Typ
Max
Unit
Test Conditions/Comments
For f < 10 MHz, ensure that the slew rate >
21 V/µs
Doubler is set in Register 4, Bit DB26
REF
IN
A biased at AV
DD
/2; ac coupling
ensures AV
DD
/2 bias
LVDS and LVPECL compatible, REF
IN
A/
REF
IN
B biased at 2.1 V; ac coupling ensures
2.1 V bias
0.4
0.4
6.9
1.4
±60
±250
125
I
CP
4.8
0.3
5.1
3
3
1.5
pF
pF
µA
µA
MHz
Single-ended reference programmed
Differential reference programmed
R
SET
= 5.1 kΩ
mA
mA
kΩ
%
%
%
Fixed
0.5 V ≤ V
CP 1
≤ V
P
− 0.5 V
0.5 V ≤ V
CP1
≤ V
P
− 0.5 V
V
CP1
= 2.5 V
1.8 V and 3.3 V compatible
V
INH
V
INL
I
INH
/I
INL
C
IN
1.5
DV
DD
0.6
±1
3.0
V
V
µA
pF
V
OH
V
OL
I
OH
AV
DD
DV
DD
, V
RF
,
V
P
, V
VCO
I
P
DV
DD
− 0.4
1.5
1.8
0.4
500
V
V
V
µA
V
3.3 V output selected
1.8 V output selected
I
OL 2
= 500 µA
3.1515
3.3
AV
DD
3.1
66
3.4485
3.3 V ± 4.5%
Voltages must equal AV
DD
5
75
mA
mA
Supply current drawn by DV
DD
plus supply
current drawn by AV
DD
See Table 6
RF output stage is programmable;
RF
OUT
B+/RF
OUT
B− powered off
Hardware power-down
Software power-down
I
VCO
I
RF
OUT
x
±
52
13/19/
25/31
1500
1950
Rev. B | Page 3 of 34
70
20/27/
34/41
mA
mA
µA
µA
ADF4355-3
Parameter
RF OUTPUT CHARACTERISTICS
VCO Frequency Range
RF Output Frequency
VCO Sensitivity
Frequency Pushing (Open-Loop)
Frequency Pulling (Open-Loop)
Harmonic Content
Second
Third
RF Output Power
4
Symbol
Min
3300
51.5625
63
22
0.54
−27
−22
−20
−12
8
3
±1
±3
−60
−30
Typ
Max
6600
6600
Unit
MHz
MHz
MHz/V
MHz/V
MHz
dBc
dBc
dBc
dBc
dBm
dBm
dB
dB
dBm
dBm
Data Sheet
Test Conditions/Comments
Fundamental VCO range
f
RF
K
V
Voltage standing wave ratio (VSWR) = 2:1
Fundamental VCO output (RF
OUT
A+)
Divided VCO output (RF
OUT
A+)
Fundamental VCO output (RF
OUT
A+)
Divided VCO output (RF
OUT
A+)
RF
OUT
A+ = 1 GHz. 7.5 nH inductor to V
RF
RF
OUT
A+/RF
OUT
A− = 4.4 GHz. 7.5 nH inductor
to V
RF
RF
OUT
A+/RF
OUT
A− = 4.4 GHz
RF
OUT
A+/RF
OUT
A− = 1 GHz to 4.4 GHz
RF
OUT
A+/RF
OUT
A− = 1 GHz, VCO = 4 GHz
RF
OUT
A+/RF
OUT
A− = 4.4 GHz, VCO = 4.4 GHz
VCO noise in open-loop conditions
RF Output Power Variation
Over Frequency
Level of Signal with Output Disabled
NOISE CHARACTERISTICS
Fundamental VCO Phase Noise
Performance
3.3 GHz Carrier
5.0 GHz Carrier
6.6 GHz Carrier
−113
−133
−135
−153
−110
−130
−132
−151
−107
−127
−129
−148
−221
−223
−116
200
−85
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fs
dBc
100 kHz offset from 3.3 GHz carrier
800 kHz offset from 3.3 GHz carrier
1 MHz offset from 3.3 GHz carrier
10 MHz offset from 3.3 GHz carrier
100 kHz offset from 5.0 GHz carrier
800 kHz offset from 5.0 GHz carrier
1 MHz offset from 5.0 GHz carrier
10 MHz offset from 5.0 GHz carrier
100 kHz offset from 6.6 GHz carrier
800 kHz offset from 6.6 GHz carrier
1 MHz offset from 6.6 GHz carrier
10 MHz offset from 6.6 GHz carrier
Normalized In-Band Phase Noise Floor
Fractional Channel
5
Integer Channel
6
Normalized 1/f Noise
7
Integrated RMS Jitter
Spurious Signals due to Phase Frequency
Detector (PFD) Frequency
1
2
PN
1_f
10 kHz offset, normalized to 1 GHz
V
CP
is the voltage at the CP
OUT
pin.
I
OL
is the output low current.
3
T
A
= 25°C; AV
DD
= DV
DD
= V
RF
= V
VCO
= V
P
= 3.3 V; prescaler = 4/5; f
REFIN
= 122.88 MHz; f
PFD
= 61.44 MHz; and f
RF
= 1650 MHz.
4
RF output power using the
EV-ADF4355-3SD1Z
evaluation board measured into a spectrum analyzer, with board and cable losses de-embedded. Unused RF output
pins are terminated in 50 Ω.
5
Use this figure to calculate the phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output, use the following formula:
−221 + 10log(f
PFD
) + 20logN. The value given is the lowest noise mode for the fractional channel.
6
Use this figure to calculate the phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output, use the following formula:
−223 + 10log(f
PFD
) + 20logN. The value given is the lowest noise mode for the integer channel.
7
The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (f
RF
)
and at a frequency offset (f) is given by PN = P
1_f
+ 10log(10 kHz/f) + 20log(f
RF
/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in the
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Embedded System
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