DS1236N-5- datasheet, PDF - EEWORLD Datasheet

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DS1236N-5-: DescriptionSupervisory Circuits; Categorysemiconductor Power management; File Size428KB，19 Pages; ManufacturerMaxim; Websitehttps://www.maximintegrated.com/en.html

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DS1236N-5- Overview

Supervisory Circuits

DS1236N-5- Parametric

Parameter Name	Attribute value
Product Category	Supervisory Circuits
Manufacturer	Maxim
RoHS	Details
Type	Voltage Supervisory
Mounting Style	Through Hole
Package / Case	PDIP-Narrow-16
Threshold Voltage	4.5 V to 5.5 V
Number of Inputs Monitored	1 Input
Output Type	Active High, Active Low
Manual Reset	Manual Reset
Battery Backup Switching	Backup
Supply Voltage - Max	5.5 V
Maximum Operating Temperature	+ 85 C
Chip Enable Signals	Chip Enable
Height	4.45 mm (Max)
Length	19.43 mm (Max)
Minimum Operating Temperature	- 40 C
Operating Supply Current	4 mA
Operating Supply Voltage	5 V
Overvoltage Threshold	4.5 V
Power Fail Detection	Yes
Reset Delay Time	150 ms
Supply Voltage - Min	4.5 V
Undervoltage Threshold	4.25 V
Watchdog Timers	Watchdog
Width	7.87 mm (Max)

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DS1236

MicroManager Chip

www.maxim-ic.com

FEATURES

Holds microprocessor in check during power

transients

Halts and restarts an out-of-control

microprocessor

Monitors pushbutton for external override

Warns microprocessor of an impending power

failure

Converts CMOS SRAM into nonvolatile

memory

Unconditionally write-protects memory when

power supply is out of tolerance

Consumes less than 100 nA of battery current

at 25°C

Controls external power switch for high

current applications

Accurate 10% power supply monitoring

Optional 5% power supply monitoring

designated DS1236-5

Provides orderly shutdown in nonvolatile

microprocessor applications

Supplies necessary control for low-power

“stop mode” in battery operated hand-held

applications

Standard 16-pin DIP or space-saving 16-pin

SOIC

Optional industrial temperature range -40°C

to +85°C

PIN ASSIGNMENT

VBAT

VCCO

VCC

GND

WC/SC

RST

PBRST

CEI

CEO

NMI

VBAT

VCCO

VCC

GND

WC/SC

RCI

RST

PBRST

CEI

CEO

NMI

16-Pin DIP (300-mil)

See Mech. Drawings Section

16-Pin SOIC (300-mil)

See Mech. Drawings Section

PIN DESCRIPTION

BAT

CCO

GND

WC/

NMI

CEO

CEI

PBRST

RST

- +3-Volt Battery Input

- Switched SRAM Supply Output

- +5-Volt Power Supply Input

- Ground

- Power-Fail (Active High)

- Power-Fail (Active Low)

- Wake-Up Control (Sleep)

- Reset Control

- Early Warning Input

- Non-Maskable Interrupt

- Strobe Input

- Chip Enable Output

- Chip Enable Input

- Pushbutton Reset Input

- Reset Output (Active Low)

- Reset Output (Active High)

DESCRIPTION

The DS1236 MicroManager Chip provides all the necessary functions for power supply monitoring, reset

control, and memory backup in microprocessor-based systems. A precise internal voltage reference and

comparator circuit monitor power supply status. When an out-of-tolerance condition occurs, the

microprocessor reset and power-fail outputs are forced active, and static RAM control unconditionally

write protects external memory. The DS1236 also provides early warning detection of a user-defined

threshold by driving a non-maskable interrupt. External reset control is provided by a pushbutton reset

1 of 19

011107

DS1236

input which is debounced and activates reset outputs. An internal watchdog timer can also force the reset

outputs to the active state if the strobe input is not driven low prior to watchdog timeout. Reset control

and wake-up/sleep control inputs also provide the necessary signals for orderly shutdown and startup in

battery backup and battery operated applications. A block diagram of the DS1236 is shown in Figure 1.

PIN DESCRIPTION

PIN NAME

BAT

CCO

DESCRIPTION

+3V battery input provides nonvolatile operation of control functions.

output for nonvolatile SRAM applications.

+5V primary power input.

Power-fail indicator, active high, used for external power switching as shown in

Figure 9.

Power-fail indicator, active low.

Wake-up and Sleep control. Invokes low-power mode.

Reset control input. Determines reset output. Normally low for NMOS processors and

high for battery backed CMOS processors.

Early warning power-fail input. This voltage sense point can be tied (via resistor

divider) to a user-selected voltage.

Non-maskable interrupt. Used in conjunction with the IN pin to indicate an impending

power failure.

Strobe input. A high-to-low transition will reset the watchdog timer, indicating that

software is still in control.

Chip enable output. Used with nonvolatile SRAM applications.

Chip enable input.

Pushbutton reset input.

Active low reset output.

Active high reset output.

WC/

NMI

CEO

CEI

PBRST

RST

PROCESSOR MODE

A distinction is often made between CMOS and NMOS processor systems. In a CMOS system, power

consumption may be a concern, and nonvolatile operation is possible by battery backing both the SRAM

and the CMOS processor. All resources would be maintained in the absence of V

. A power-down reset

is not issued since the low-power mode of most CMOS processors (Stop) is terminated with a Reset. A

pulsed interrupt (

NMI

) is issued to allow the CMOS processor to invoke a sleep mode to save power. For

this case, a power-on reset is desirable to wake up and initialize the processor. The CMOS mode is

invoked by connecting RC to V

CCO

An NMOS processor consumes more power, and consequently may not be battery backed. In this case, it

is desirable to notify the processor of a power-fail, then keep it in reset during the loss of V

. This avoids

intermittent or aberrant operation. On power-up, the processor will continue to be reset until V

reaches

an operational level to provide an orderly start. The NMOS mode is invoked by connecting RC to ground.

2 of 19

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