Programmable System-on-Chip (PSoC )
General Description
PSoC
®
4: PSoC 4100 Family
Datasheet
®
PSoC
®
4 is a scalable and reconfigurable platform architecture for a family of mixed-signal programmable embedded system
controllers with an ARM
®
Cortex™-M0 CPU. It combines programmable and reconfigurable analog and digital blocks with flexible
automatic routing. The PSoC 4100 product family, based on this platform, is a combination of a microcontroller with digital program-
mable logic, high-performance analog-to-digital conversion, opamps with Comparator mode, and standard communication and timing
peripherals. The PSoC 4100 products will be fully upward compatible with members of the PSoC 4 platform for new applications and
design needs. The programmable analog and digital sub-systems allow flexibility and in-field tuning of the design.
Features
32-bit MCU Sub-system
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Timing and Pulse-Width Modulation
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24-MHz ARM Cortex-M0 CPU with single-cycle multiply
Up to 32 kB of flash with Read Accelerator
Up to 4 kB of SRAM
Four 16-bit timer/counter pulse-width modulator (TCPWM)
blocks
Center-aligned, Edge, and Pseudo-random modes
Comparator-based triggering of Kill signals for motor drive and
other high reliability digital logic applications
Programmable Analog
■
Two opamps with reconfigurable high-drive external and
high-bandwidth internal drive and Comparator modes and ADC
input buffering capability
12-bit 806 ksps SAR ADC with differential and single-ended
modes and Channel Sequencer with signal averaging
Two current DACs (IDACs) for general-purpose or capacitive
sensing applications on any pin
Two low-power comparators that operate in Deep Sleep
Up to 36 Programmable GPIOs
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Any GPIO pin can be CapSense, LCD, analog, or digital
Drive modes, strengths, and slew rates are programmable
Five different packages
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■
48-pin TQFP, 44-pin TQFP, 40-pin QFN, 35-ball WLCSP, and
28-pin SSOP package
35-ball WLCSP package is shipped with I
2
C Bootloader in
Flash
Low Power 1.71-V to 5.5-V operation
■
■
20-nA Stop Mode with GPIO pin wakeup
Hibernate and Deep Sleep modes allow wakeup-time versus
power trade-offs
Extended Industrial Temperature Operation
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–40 °C to + 105 °C operation
Capacitive Sensing
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■
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Cypress CapSense Sigma-Delta (CSD) provides best-in-class
SNR (>5:1) and water tolerance
Cypress supplied software component makes capacitive
sensing design easy
Automatic hardware tuning (SmartSense™)
PSoC Creator Design Environment
■
Integrated Development Environment provides schematic
design entry and build (with analog and digital automatic
routing)
Applications Programming Interface (API Component) for all
fixed-function and programmable peripherals
■
Segment LCD Drive
■
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Industry Standard Tool Compatibility
■
LCD drive supported on all pins (common or segment)
Operates in Deep Sleep mode with 4 bits per pin memory
After schematic entry, development can be done with
ARM-based industry-standard development tools
Serial Communication
■
Two independent run-time reconfigurable serial communi-
cation blocks (SCBs) with reconfigurable I
2
C, SPI, or UART
functionality
Cypress Semiconductor Corporation
Document Number: 001-87220 Rev. *J
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised July 10, 2017
PSoC
®
4: PSoC 4100 Family
Datasheet
More Information
Cypress provides a wealth of data at
www.cypress.com
to help you to select the right PSoC device for your design, and to help you
to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the knowledge base article
KBA86521, How to Design with PSoC 3, PSoC 4, and PSoC 5LP.
Following is an abbreviated list for PSoC 4:
■
■
■
Overview:
PSoC Portfolio, PSoC Roadmap
Product Selectors:
PSoC 1, PSoC 3, PSoC 4, PSoC 5LP
In addition, PSoC Creator includes a device selection tool.
Application notes: Cypress offers a large number of PSoC
application notes covering a broad range of topics, from basic
to advanced level. Recommended application notes for getting
started with PSoC 4 are:
❐
AN79953:
Getting Started With PSoC 4
❐
AN88619:
PSoC 4 Hardware Design Considerations
❐
AN86439:
Using PSoC 4 GPIO Pins
❐
AN57821:
Mixed Signal Circuit Board Layout
❐
AN81623:
Digital Design Best Practices
❐
AN73854:
Introduction To Bootloaders
❐
AN89610:
ARM Cortex Code Optimization
❐
AN90071:
CY8CMBRxxx CapSense Design Guide
■
Technical Reference Manual (TRM) is in two documents:
❐
Architecture TRM
details each PSoC 4 functional block.
❐
Registers TRM
describes each of the PSoC 4 registers.
Development Kits:
❐
CY8CKIT-042,
PSoC 4 Pioneer Kit, is an easy-to-use and
inexpensive development platform. This kit includes
connectors for Arduino™ compatible shields and Digilent®
Pmod™ daughter cards.
❐
CY8CKIT-049
is a very low-cost prototyping platform. It is a
low-cost alternative to sampling PSoC 4 devices.
❐
CY8CKIT-001
is a common development platform for any
one of the PSoC 1, PSoC 3, PSoC 4, or PSoC 5LP families
of devices.
The
MiniProg3
device provides an interface for flash
programming and debug.
■
PSoC Creator
PSoC Creator
is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design
of PSoC 3, PSoC 4, and PSoC 5LP based systems. Create designs using classic, familiar schematic capture supported by over 100
pre-verified, production-ready PSoC Components; see the
list of component datasheets.
With PSoC Creator, you can:
1. Drag and drop component icons to build your hardware
3. Configure components using the configuration tools
system design in the main design workspace
4. Explore the library of 100+ components
2. Codesign your application firmware with the PSoC hardware,
5. Review component datasheets
using the PSoC Creator IDE C compiler
Figure 1. Multiple-Sensor Example Project in PSoC Creator
1
2
3
5
Document Number: 001-87220 Rev. *J
Page 2 of 43
4
PSoC
®
4: PSoC 4100 Family
Datasheet
Contents
Functional Definition........................................................ 5
CPU and Memory Subsystem ..................................... 5
System Resources ...................................................... 5
Analog Blocks.............................................................. 6
Fixed Function Digital.................................................. 7
GPIO ........................................................................... 7
Special Function Peripherals....................................... 8
Pinouts .............................................................................. 9
Power............................................................................... 15
Unregulated External Supply..................................... 15
Regulated External Supply........................................ 16
Development Support .................................................... 17
Documentation .......................................................... 17
Online ........................................................................ 17
Tools.......................................................................... 17
Electrical Specifications ................................................ 18
Absolute Maximum Ratings....................................... 18
Device-Level Specifications ...................................... 18
Analog Peripherals ....................................................
Digital Peripherals .....................................................
Memory .....................................................................
System Resources ....................................................
Ordering Information......................................................
Part Numbering Conventions ....................................
Packaging........................................................................
Acronyms ........................................................................
Document Conventions .................................................
Units of Measure .......................................................
Revision History .............................................................
Sales, Solutions, and Legal Information ......................
Worldwide Sales and Design Support.......................
Products ....................................................................
PSoC® Solutions ......................................................
Cypress Developer Community.................................
Technical Support .....................................................
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Document Number: 001-87220 Rev. *J
Page 3 of 43
PSoC
®
4: PSoC 4100 Family
Datasheet
Figure 2. Block Diagram
CPU Subsystem
PSoC 4100
32-bit
SW D
C ortex
M0
24 M H z
FAST M U L
N VIC , IR Q M X
FLASH
U p to 32 kB
R ead Accelerator
SR AM
U p to 4 kB
SR AM C ontroller
ROM
4 kB
R O M C ontroller
AH B -Lite
System R esources
Pow er
Sleep C ontrol
W IC
PO R
LVD
R EF
BO D
PW R SYS
N VLatches
C lock
C lock C ontrol
WDT
IM O
ILO
System Interconnect (Single Layer AHB)
Peripherals
PC LK
Peripheral Interconnect (M M IO)
Program m able
Analog
4x TCPWM
2x SCB-
I2C/SPI/UART
IOSS GPIO (
5x ports)
R eset
R eset C ontrol
XR ES
Test
D FT Logic
D FT Analog
x1
SM X
CTBm
x1
2x O pAm p
Port Interface & D igital System Interconnect (D SI)
Pow er M odes
Active/Sleep
D eep Sleep
H ibernate
H igh Speed I/O M atrix
36x G PIO s
IO Subsystem
The PSoC 4100 devices include extensive support for
programming, testing, debugging, and tracing both hardware
and firmware.
The ARM Serial_Wire Debug (SWD) interface supports all
programming and debug features of the device.
Complete debug-on-chip functionality enables full device
debugging in the final system using the standard production
device. It does not require special interfaces, debugging pods,
simulators, or emulators. Only the standard programming
connections are required to fully support debug.
The PSoC Creator Integrated Development Environment (IDE)
provides fully integrated programming and debug support for the
PSoC 4100 devices. The SWD interface is fully compatible with
industry standard third party tools. With the ability to disable
debug features, with very robust flash protection, and by allowing
customer-proprietary functionality to be implemented in on-chip
programmable blocks, the PSoC 4100 family provides a level of
security not possible with multi-chip application solutions or with
microcontrollers.
The debug circuits are enabled by default and can only be
disabled in firmware. If not enabled, the only way to re-enable
them is to erase the entire device, clear flash protection, and
reprogram the device with new firmware that enables debugging.
Additionally, all device interfaces can be permanently disabled
(device security) for applications concerned about phishing
attacks due to a maliciously reprogrammed device or attempts to
defeat security by starting and interrupting flash programming
sequences. Because all programming, debug, and test inter-
faces are disabled when maximum device security is enabled,
PSoC 4100 with device security enabled may not be returned for
failure analysis. This is a trade-off the PSoC 4100 allows the
customer to make.
Document Number: 001-87220 Rev. *J
LCD
SAR AD C
(12-bit)
Page 4 of 43
2x LP Comparator
Capsense
PSoC
®
4: PSoC 4100 Family
Datasheet
Functional Definition
CPU and Memory Subsystem
CPU
System Resources
Power System
The Cortex-M0 CPU in PSoC 4100 is part of the 32-bit MCU
subsystem, which is optimized for low power operation with
extensive clock gating. It mostly uses 16-bit instructions and
executes a subset of the Thumb-2 instruction set. This enables
fully compatible binary upward migration of the code to higher
performance processors such as the Cortex-M3 and M4, thus
enabling upward compatibility. The Cypress implementation
includes a hardware multiplier that provides a 32-bit result in one
cycle. It includes a nested vectored interrupt controller (NVIC)
block with 32 interrupt inputs and also includes a Wakeup
Interrupt Controller (WIC), which can wake the processor up
from Deep Sleep mode allowing power to be switched off to the
main processor when the chip is in Deep Sleep mode. The
Cortex-M0 CPU provides a Non-Maskable Interrupt input (NMI),
which is made available to the user when it is not in use for
system functions requested by the user.
The CPU also includes a debug interface, the serial wire debug
(SWD) interface, which is a two-wire form of JTAG; the debug
configuration used for PSoC 4100 has four break-point
(address) comparators and two watchpoint (data) comparators.
Flash
The power system is described in detail in the section
Power on
page 15.
It provides assurance that voltage levels are as
required for each respective mode and either delay mode entry
(on power-on reset (POR), for example) until voltage levels are
as required for proper function or generate resets (brown-out
detect (BOD)) or interrupts (low-voltage detect (LVD)). The
PSoC 4100 operates with a single external supply over the range
of 1.71 V to 5.5 V and has five different power modes, transitions
between which are managed by the power system. PSoC 4100
provides Sleep, Deep Sleep, Hibernate, and Stop low-power
modes.
Clock System
The PSoC 4100 clock system is responsible for providing clocks
to all subsystems that require clocks and for switching between
different clock sources without glitching. In addition, the clock
system ensures that no metastable conditions occur.
The clock system for PSoC 4100 consists of the internal main
oscillator (IMO) and the internal low-power oscillator (ILO) and
provision for an external clock.
Figure 3. PSoC 4100 MCU Clocking Architecture
IMO
EXTCLK
HFCLK
PSoC 4100 has a flash module with a flash accelerator tightly
coupled to the CPU to improve average access times from the
flash block. The flash block is designed to deliver 0 wait-state
(WS) access time at 24 MHz. Part of the flash module can be
used to emulate EEPROM operation if required.
The PSoC 4200 Flash supports the following flash protection
modes at the memory subsystem level:
■
■
ILO
LFCLK
Open: No Protection.
Factory default mode in which the
product is shipped.
Protected: User may change from Open to Protected.
This
mode disables Debug interface accesses. The mode can be
set back to Open but only after completely erasing the Flash.
Kill: User may change from Open to Kill.
This mode disables
all Debug accesses. The part cannot be erased externally, thus
obviating the possibility of partial erasure by power interruption
and potential malfunction and security leaks. This is an irrecvo-
cable mode.
HFCLK
Prescaler
SYSCLK
■
Analog
Divider
Peripheral
Dividers
SAR clock
PERXYZ _ CLK
In addition, row-level Read/Write protection is also supported to
prevent inadvertent Writes as well as selectively block Reads.
Flash Read/Write/Erase operations are always available for
internal code using system calls.
SRAM
SRAM memory is retained during Hibernate.
SROM
A supervisory ROM that contains boot and configuration routines
is provided.
The HFCLK signal can be divided down (see
PSoC 4100 MCU
Clocking Architecture)
to generate synchronous clocks for the
analog and digital peripherals. There are a total of 12 clock
dividers for PSoC 4100, each with 16-bit divide capability. The
analog clock leads the digital clocks to allow analog events to
occur before digital clock-related noise is generated. The 16-bit
capability allows a lot of flexibility in generating fine-grained
frequency values and is fully supported in PSoC Creator.
Document Number: 001-87220 Rev. *J
Page 5 of 43
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