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74LVC161284TTR

Description
Bus Transceivers Hi-Spd IEEE1284 Tran
CategoryAnalog mixed-signal IC    Drivers and interfaces   
File Size216KB,11 Pages
ManufacturerSTMicroelectronics
Websitehttp://www.st.com/
Environmental Compliance
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74LVC161284TTR Overview

Bus Transceivers Hi-Spd IEEE1284 Tran

74LVC161284TTR Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSTMicroelectronics
Parts packaging codeTSSOP
package instructionTSSOP,
Contacts48
Reach Compliance Codecompliant
ECCN codeEAR99
Factory Lead Time16 weeks
Differential outputNO
Number of drives8
Input propertiesSCHMITT TRIGGER
Interface integrated circuit typeLINE TRANSCEIVER
Interface standardsIEEE 1284
JESD-30 codeR-PDSO-G48
JESD-609 codee3
length12.5 mm
Humidity sensitivity level3
Number of functions1
Number of terminals48
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Maximum receive delay9 ns
Number of receiver bits8
Maximum seat height1.2 mm
Maximum supply voltage3.6 V
Minimum supply voltage3 V
Nominal supply voltage3.3 V
Supply voltage 1-max5.5 V
Mains voltage 1-minute3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
maximum transmission delay9 ns
width6.1 mm
Base Number Matches1
74LVC161284
LOW VOLTAGE HIGH SPEED IEEE1284 TRANSCEIVER
s
s
HIGH SPEED: t
PD
= 9ns (MAX.) at V
CC
= 3V
LOW POWER DISSIPATION:
I
CC
=20µA (MAX) at V
CC
=3.6V T
A
=85°C
TTL COMPATIBLE INPUTS
V
IH
=2V (MIN) V
IL
=0.8(MAX)
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 3.0V to 3.6V
A PORT HAVE STANDARD 4mA TOTEM
POLE OUTPUT
B PORT HIGH DRIVE SOURCE/SINK
CAPABILITY OF 14mA
SUPPORT IEEE STD 1284-I (LEVEL 1 TYPE)
AND IEEE STD 1284-II (LEVEL 2 TYPE) FOR
BIDIRECTIONAL PARALLEL
COMMUNICATIONS BETWEEN PERSONAL
COMPUTER ANT PRINTING PERIPHERALS
TRANSLATION CAPABILITY ALLOW
OUTPUTS ON CABLE SIDE TO INTERFACE
WITH 5V SIGNAL
PULL-UP RESISTOR INTEGRATED ON ALL
OPEN-DRAIN OUTPUT ELIMINATE THE
NEED FOR DISCRETE RESISTOR
REPLACE THE FUNCTION OF TWO
74LVC1284 DEVICES
ORDER CODES
PACKAGE
TSSOP
TUBE
T&R
74LVC161284TTR
TSSOP
s
s
s
s
s
PIN CONNECTION
s
s
s
DESCRIPTION
The 74LVC161284 contains eight high speed non
inverting bidirectional buffers and eleven control/
status non-inverting buffers with open drain
outputs fabricated in silicon gate C
2
MOS
technology. It’s intended to provide a standard
signaling method for a bi-direction parallel
peripheral in an Extended Capabilities Port Mode
(ECP). The HD (Active HIGH) input pin enables
the Cable port to switch from Open Drain to a high
drive totem pole output, capable of sourcing 14mA
on all thirteen buffer and 84mA on PERI LOGIC
OUTPUT buffer. The DIR input determines the
direction of data flow on the bidirectional buffers.
DIR (Active HIGH) enables data flow from A port
to B port. DIR (Active LOW) enables data flow
from B port to A port. It is available in the
commercial temperature range.
May 2003
1/11

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