PSMN1R5-25YL
N-channel TrenchMOS logic level FET
Rev. 01 — 16 June 2009
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
industrial and communications applications.
1.2 Features and benefits
High efficiency due to low switching
and conduction losses
Suitable for logic level gate drive
sources
1.3 Applications
Class-D amplifiers
DC-to-DC converters
Motor control
Server power supplies
1.4 Quick reference data
Table 1.
V
DS
I
D
P
tot
Quick reference
Conditions
T
mb
= 25 °C; V
GS
= 10 V;
see
Figure 1;
T
mb
= 25 °C; see
Figure 2
[1]
Min
-
-
-
Typ
-
-
-
Max
25
100
109
Unit
V
A
W
drain-source voltage T
j
≥
25 °C; T
j
≤
150 °C
drain current
total power
dissipation
gate-drain charge
Symbol Parameter
Dynamic characteristics
Q
GD
V
GS
= 4.5 V; I
D
= 10 A;
V
DS
= 12 V; see
Figure 14;
see
Figure 15
V
GS
= 4.5 V; I
D
= 10 A;
V
DS
= 12 V; see
Figure 14;
see
Figure 15
V
GS
= 10 V; I
D
= 15 A;
T
j
= 25 °C
-
9.2
-
nC
Q
G(tot)
total gate charge
-
36
-
nC
Static characteristics
R
DSon
drain-source
on-state resistance
-
1.13
1.5
mΩ
[1]
Continuous current is limited by package.
Nexperia
PSMN1R5-25YL
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2.
Pin
1
2
3
4
mb
S
S
S
G
D
Pinning information
Symbol
Description
source
source
source
gate
mounting base; connected to
drain
mbb076
Simplified outline
mb
Graphic symbol
D
G
S
1 2 3 4
SOT669
(LFPAK)
3. Ordering information
Table 3.
Ordering information
Package
Name
PSMN1R5-25YL
LFPAK
Description
plastic single-ended surface-mounted package (LFPAK); 4 leads
Version
SOT669
Type number
4. Limiting values
Table 4.
Symbol
V
DS
V
DGR
V
GS
I
D
I
DM
P
tot
T
stg
T
j
I
S
I
SM
E
DS(AL)S
Limiting values
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
peak drain current
total power dissipation
storage temperature
junction temperature
source current
peak source current
T
mb
= 25 °C;
t
p
≤
10 µs; pulsed; T
mb
= 25 °C
[1]
V
GS
= 10 V; T
mb
= 100 °C; see
Figure 1
V
GS
= 10 V; T
mb
= 25 °C; see
Figure 1
t
p
≤
10 µs; pulsed; T
mb
= 25 °C; see
Figure 3
T
mb
= 25 °C; see
Figure 2
[1]
[1]
Conditions
T
j
≥
25 °C; T
j
≤
150 °C
T
j
≥
25 °C; T
j
≤
150 °C; R
GS
= 20 kΩ
Min
-
-
-20
-
-
-
-
-55
-55
-
-
-
Max
25
25
20
100
100
815
109
150
150
100
815
290
Unit
V
V
V
A
A
A
W
°C
°C
A
A
mJ
In accordance with the Absolute Maximum Rating System (IEC 60134).
Source-drain diode
Avalanche ruggedness
non-repetitive
V
GS
= 10 V; T
j(init)
= 25 °C; I
D
= 100 A; V
sup
≤
25 V;
drain-source avalanche R
GS
= 50
Ω;
unclamped
energy
[1]
Continuous current is limited by package.
PSMN1R5-25YL_1
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 01 — 16 June 2009
2 of 13
Nexperia
PSMN1R5-25YL
N-channel TrenchMOS logic level FET
250
I
D
(A)
200
003aac900
120
P
der
(%)
80
03aa15
150
100
(1)
40
50
0
0
50
100
150
T
mb
(°C)
200
0
0
50
100
150
T
mb
(°C)
200
Fig 1.
Continuous drain current as a function of
mounting base temperature
Fig 2.
Normalized total power dissipation as a
function of mounting base temperature
003aac901
10
4
I
D
(A)
10
3
Limit R
DSon
= V
DS
/ I
D
10
µs
10
2
(1)
100
µs
10
DC
1 ms
10 ms
100 ms
10
10
2
1
10
-1
1
V
DS
(V)
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PSMN1R5-25YL_1
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 01 — 16 June 2009
3 of 13
Nexperia
PSMN1R5-25YL
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 5.
Symbol
R
th(j-mb)
Thermal characteristics
Parameter
Conditions
Min
-
Typ
0.5
Max
1.1
Unit
K/W
thermal resistance from see
Figure 4
junction to mounting
base
10
Z
th(j-mb)
(K/W)
1
δ
= 0.5
10
-1
003aac456
0.2
0.1
0.05
0.02
P
δ
=
t
p
T
10
-2
single shot
t
p
T
t
10
-3
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
t
p
(s)
1
Fig 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration
PSMN1R5-25YL_1
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 01 — 16 June 2009
4 of 13
Nexperia
PSMN1R5-25YL
N-channel TrenchMOS logic level FET
6. Characteristics
Table 6.
Symbol
V
(BR)DSS
V
GS(th)
Characteristics
Parameter
drain-source
breakdown voltage
gate-source threshold
voltage
Conditions
I
D
= 250 µA; V
GS
= 0 V; T
j
= 25 °C
I
D
= 250 µA; V
GS
= 0 V; T
j
= -55 °C
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 25 °C;
see
Figure 11;
see
Figure 12
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 150 °C;
see
Figure 12
I
D
= 1 mA; V
DS
= V
GS
; T
j
= -55 °C;
see
Figure 12
I
DSS
I
GSS
R
DSon
drain leakage current
gate leakage current
drain-source on-state
resistance
V
DS
= 25 V; V
GS
= 0 V; T
j
= 25 °C
V
DS
= 25 V; V
GS
= 0 V; T
j
= 150 °C
V
GS
= 16 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= -16 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= 4.5 V; I
D
= 15 A; T
j
= 25 °C
V
GS
= 10 V; I
D
= 15 A; T
j
= 150 °C;
see
Figure 13
V
GS
= 10 V; I
D
= 15 A; T
j
= 25 °C
R
G
Q
G(tot)
gate resistance
total gate charge
f = 1 MHz
I
D
= 10 A; V
DS
= 12 V; V
GS
= 10 V;
see
Figure 14;
see
Figure 15
I
D
= 0 A; V
DS
= 0 V; V
GS
= 10 V
I
D
= 10 A; V
DS
= 12 V; V
GS
= 4.5 V;
see
Figure 14;
see
Figure 15
Q
GS
Q
GS(th)
Q
GS(th-pl)
Q
GD
V
GS(pl)
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
gate-source charge
pre-threshold
gate-source charge
post-threshold
gate-source charge
gate-drain charge
gate-source plateau
voltage
input capacitance
output capacitance
reverse transfer
capacitance
turn-on delay time
rise time
turn-off delay time
fall time
V
DS
= 12 V; R
L
= 0.5
Ω;
V
GS
= 4.5 V;
R
G(ext)
= 4.7
Ω
V
DS
= 12 V; see
Figure 14
V
DS
= 12 V; V
GS
= 0 V; f = 1 MHz;
T
j
= 25 °C; see
Figure 16
I
D
= 10 A; V
DS
= 12 V; V
GS
= 4.5 V;
see
Figure 14;
see
Figure 15
Dynamic characteristics
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
76
71
36
12.3
7.8
4.5
9.2
2.4
4830
1280
465
50
97
72
36
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
nC
nC
nC
nC
nC
nC
nC
V
pF
pF
pF
ns
ns
ns
ns
Min
25
22
1.3
0.65
-
-
-
-
-
-
-
-
-
Typ
-
-
1.7
-
-
-
-
-
-
1.61
-
1.13
0.77
Max
-
-
2.15
-
2.45
1
100
100
100
2.2
2.6
1.5
-
Unit
V
V
V
V
V
µA
µA
nA
nA
mΩ
mΩ
mΩ
Ω
Static characteristics
PSMN1R5-25YL_1
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 01 — 16 June 2009
5 of 13
Automotive Electronics
京公网安备 11010802033920号
EEWORLD
