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MOTOROLA
-
Freescale Semiconductor, Inc.
Order this document
BR5091D
by
SEMICONDUCTOR
TECHNICAL DATA
.—
.“.,.,
:,,
.:..$
1.
.,.
3
:
MC68882
Floating-Point
Coprocessor
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Freescale Semiconductor, Inc...
The MC68882 floating-point
coprocessor fully implements
the IEEE Standard for Binary Floatin~_+’’,i~’C
Point Arithmetic
(ANSI-IEEE Standard 754-1985) for use with the Motorola M68000 Family of ,,~f@&~i$
processors. An upgrade of the MC68881, it is pin and software compatible with an optimiz$d ~~$~
interface providing in excess of 1.5 times the performance
of the MC68881. It is implem~~~,,
ui;ng
VLSI technology
to give systems designers the highest possible functionality
in a ph~:W&~&mali
.!.},.,
~,,,*.,,,*
device.
\$.i,,, >$
Intended primarily for use as a coprocessor to the MC68020 or MC68030 32-bi~,~$&@’rocessor
unit (MPU), the MC68882 provides a logical extension to the main MPU integer ~~$~~rocessing
capabilities.
This extension is achieved by providing a very high performan~~oatlng-point
arith-
metic unit and a set of floating-point
data registers which are analogoust$~~t~
&se of the integer
data registers. The MC68882 instruction set is a natural extension of a~j $afi~r members of the
M68000 Family, and it supports all of the addressing modes
of the ~$’~~~.
Due to the flexible
bus interface of the M68000 Family, the MC68882 can be used wj~~ ari~,of the MPU devices of the
M68000 Family and as a peripheral to non-M68000 processors{,{~~ :&+,
.,$>.*), $
. >.
The major features of the MC68882 are:
.:.?:
. :;:,>..+
..
q
Eight general purpose floating-point
data register%!,,,*..l,k*,
?P~M.8’tipporting a full 80-bit extended
,,**.
precision real data format (a 64-bit mantissa plus ~~,~~ bit, and a 15-bit signed exponent).
“ -~,
. ,J
unit to allow very fast cal$ula~~ons~ with intermediate
precision greater
.3*$;; .
than the extended precision format.
“ “:*\.
etc.).
.
A
67-bit barrel shifter for high-speed s~jfl~~b d~erations (for normalizing
o Special purpose hardware for high-#~~&k~”&nversion
of binary real memory operands to and
q
A 67-bit arithmetic
from” the internal
. Reduced
.
.
.
q
extended
forma~J~$,,~#>
to increase throughput.
coprocessor
instructions,
interfac$~~wad
includ~n@~~5Jarith metic operations.
~,, ,...>.{,.,
\
‘~.
Full conformation
to the.#~$~}FEE
754 standard, including all requirements
and suggestions,
.’:’!..,
Support of functionsA@”%+,@#ned by the IEEE standard, including a full set of trigonometric
and transcendenta~,:t ‘.’:*w, ,:s
f&ct~ns,
.
Seven data
type$$.’b~e,
word and long word
integers; single, double,
~$%
,:+
real number$),$ndp-acked
binary coded decimal string real numbers.
Twenty-t~t~&$,~~tants
available
in the on-chip
ROM, including
Virtual @&@@rY/machine
operations.
and interrupt
handling.
and extended
precision
Forty-six
q
q
q
n, e, and powers
of 10,
Effi~~<#~~eChanisms
for procedure calls, context switches,
. ..f\.
. Q&fiC&~~ent instruction execution with the main processor.
,4*j&QQlurrent
instruction execution of multiple floating-point
instructions.
.‘+:~:,$
,~,
“:%.,use with any host processor, on an 8-, 16-, or 32-bit data bus.
.,,,,:., *I!<*
$fi~:
~>+~~$.il>
Y}i:,,,,
$
I*>
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,.
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:?,
‘:.?
>
This document contains information
on a new product. Specifications and information
herein are subject to change without notice.
@MoToRoLA
INC.,
1988
.
. ..
..
,.
..
.
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
@
BRW/Rev.
3
-
Freescale Semiconductor, Inc.
THE COPROCESSOR
CONCEPT
HARDWARE
OVERVIEW
Freescale Semiconductor, Inc...
The MC68882 functions as a coprocessor in systems
where the MC68020 or MC68030 is the main processor
via the M68000 coprocessor interface. It functions as a
peripheral processor in systems where the main
proces-
sor is the MC68000, MC68008, or MC68010.
The MC68882 utilizes the M68000 Family coprocessor
interface to provide a logical extension of the MC68020
or MC68030 registers and instruction
set in a manner
which is transparent to the programmer.
The program-
mer perceives the MPU/FPCP execution model as if both
devices are implemented
on one chip. A fundamental
goal of the M68000 Family coprocessor
interface is to
provide the programmer
with an execution model based
upon sequential instruction
execution by the MC68020
or MC68030 and the MC68882. For optimum
perform-
ante, however, the coprocessor interface allows concur-
rent operations
in the MC68882 with respect to the
MC68020 or MC68030 whenever possible. In order to sim-
plify the programmer’s
model, the coprocessor interface
is designed to emulate, as closely as possible, non-con-
current operation between the MC68020 or MC68030 and
the MC68882.
The MC68882 is a non-DMA type coprocessor which
uses a subset of the general purpose coprocessor inter-
face supported by the MC68020 or MC68030. Features of
the interface implemented
in the MC68882 are as follows:
The MC68882 is a high performance floating-point
de-
vice designed to interface with the MC68020 or MC68030
as a coprocessor. This device fully supports the MC68020
or
MC68030 virtual machine architecture
and is imple-
mented in HCMOS, Motorola’s
low power, small geom-
etry process. This process allows CMOS and HMOS (high
density NMOS) gates to be combined on the sa,,~<~~evice.
CMOS structures are used where speed a~@,l~~,~ower
is required, and HMOS structures are use~, W%re mini-
. ::,t. .,;.i.
~ +
~$~
mum silicon area is desired. Using t~,~ W&Whology in-
..,,.’~>
creases speed performance
whi~g%~!$g
low power
consumption,
yet still confines th~’~~~~~~1
to ., reason-
a
,“..t+~
,,,,’.J-,$\\
j ‘~.s,~;.
I..\..
ably small die size.
,*~-. !~ ‘k
The MC68882 can also Qf ~~,$as
a peripheral
pro-
cessor in systems where t@@~~C68020 or MC68030 is not
the main processor (e,&};,W&OOO, MC68008, MC68010).
The configuration
o~$~ ,@68882
as a peripheral
pro-
cessor or coprocqs$@~’m#y be completely transparent to
~,..s ‘
,,,‘,~
user software (i.e.;%~~’%ame object code maybe executed
in either co~~$~::atfon).
The ar~&$,~~’re
of the MC68882 appears to the user
as a lo~i~.,1, e~tension of the M68000 Family architecture,
Beca~$@o~the coupling of the coprocessor interface, the
,p
p
\.;
~~fi80’*
or MC68030 programmer can view the MC68882
.,.~eg$~ters as though
the registers are resident in the
#“~68020
or MC68030. Thus, a MC68020 or MC68030 and
‘ “$~e~ MC68882 device pair functions as one processor with
. The main processor(s) and MC68882 communicat~~~~jw’
~**.~~ eight integer data registers, eight address registers, and
via standard M68000 bus cycles.
.!>
eight floating-point
data registers supporting seven float-
. The main processor(s) and MC68882 cO.~mUti:i-
ing-point and integer data types.
cations are not dependent
upon the a~@:a&cture
The MC68882 programming
model is shown in Figures
of the individual devices (e.g., instruc@~$~ip&s
or
1 through 6 and consists of the following:
V;>!]*Q,
caches, addressing modes).
“..i.
, ~).:t.x,
‘:. .*
+f{”i,~
q
Eight 80-bit floating-point
data registers (FPO-FP7).
q
The main processor(s)
and MC6@~~~@ay operate
These registers are analogous to the integer data
,“~.!.. ,.~\
. ~’x$:’~kl,
~:.,?..:,..
{,m
‘+<
at different clock speeds.
.?,$:,,,“’’”.:
7*
registers (DO-D7) and are completely general pur-
q
MC68882 instructions
util,i~~,a$~~ddressing modes
pose (i.e., any instruction can use any register).
provided by the main @#o<$#&or.
e A 32-bit control register that contains enable bits
~:+ ~\;~,
~’ ., *,*$
q
All effective addreqqb~~q’y%calcu lated by the main
for each class of exception trap, and mode bits to
processor at th~t~~~si~
of the coprocessor.
set the user-selectable
rounding
and precision
modes.
q
All data tran~fdxk$:~~e performed
by the main pro-
cessor at ~~’~we~uest of the MC68882.
.*:\,j+p,\:t
i ,
q
Overla~@
ft’bncurrent)
instruction execution en-
han~,~~?~bughput
while maintaining
the pro-
g&~t@~*~r’s model
of sequential
instruction
~f3%$BNt
ion,
q
..
,..-
A 32-bit status register that contains floating-point
condition codes, quotient bits, and exception sta-
tus information.
,,:,~’~~~~~dprocessor detection of exceptions which require
‘ ,J:gt,
........
a trap to be taken are serviced by the main pro-
8::’i\iJ..,tJ?~.
.
..:..$,,>9. cessor at the request of the MC68882.
~lt~.
.;.
>
q
Support
of virtual memory/virtual
machine sys-
terns is provided via the FSAVE and FRESTORE
instructions.
q
Up to eight coprocessor
simultaneously.
Multiple
type are allowed.
may reside in a system
coprocessor
of the same
.
Systems
may use software
emulation
of the
MC68882 without reassembling
or relinking user
software.
A 32-bit instruction
address register that contains
the main processor memory address of the last
floating-point
instruction
that was executed. This
address is used in exception handling to locate the
instruction that caused the exception,
The connection between the MC68020 or MC68030 and
the MC68882 is a simple extension of the M68000 bus
interface. The MC68882 is connected as a coprocessor to
the MC68020 or MC68030, and the selection
of the
MC68882 is based on a chip select which is decoded from
the MC68020 or MC68030 function codes and address
bus. Figure 7 illustrates the MPU/coprocessor
configu-
ration.
As shown in Figure 8, the MC68882 is internally divided
into three processing
elements:
the bus interface unit
q
,. -,
,~,
‘./
For More Information On This Product,
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MOTOROU
2
M~
BRW/Rev.
3
Freescale Semiconductor, Inc.
7
I
I
\
I
r
I
t
I
I
,
FPO
FP1
FP2
FP3
FP4
FP5
FLOATING POINT
DATA REGISTERS
I
Freescale Semiconductor, Inc...
~
ROUNOING
00
01
10
11
MOOE:
TO NEAREST
TOWARD ZERO
TOWARD MINUS INFINIW
TOWARD PLUS INFINIV
ROUNDING PRECISION:
00 EXTENDED
01 SINGLE
10 DOUBLE
11 (UNDEFINEO, RESERVEO)
Figure
3. Mode
Control
B~e
For More Information On This Product,
Go to: www.freescale.com
MC-
BRW/Rev,
MOTOROM
3
3
Freescale Semiconductor, Inc.
31
[
30
o
29
2a
27
N
26
z
25
I
24
NAN
NOT A NUMBER
lNFINl~
ZERO
NEGATIVE
OR UNORDERED
Figure 4. Condition Code B~e
23
22
21
20
19
QUOTIENT
la
17
16
I
I s
1
Freescale Semiconductor, Inc...
Figure 5, Quotient
B~e
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
(BIU), the conversion unit (CU), and the arithmetic proc-
cycle. (The function codes are generated by the M68000
essing unit (APU). The BIU communicates
with the
Family processors to identify eight separate address
MC68620 or MC68030, the CU performs data conversion
spaces.)” Thus, the memory-mapped
coprocessor
inter-
For binary real data formats, and the APU executes all
face registers do not infringe upon instruction
or data
MC68882 instructions.
address spaces. The MC68020 or MC68030 places a co-
The BIU contains the coprocessor
interface registers
processor ID field from the coprocessor instruction onto
three of the upper address lines during coprocessor ac-
(CIRS). In addition to these registers, the register select
and DSACK timing control logic is contained in the BIU.
cesses. This ID, along with the CPU address space func-
Finally, the status flags used to monitor the status of
tion code, is decoded to select one of eight coprocessor
communications
with the main processor are contained
in the system.
~
~~~.~l,
in the BIU.
Since the coprocessor interface protocol is ba~~wlely
The CU contains special purpose hardware that per-
on bus transfers, the protocol is easily ernu~?~q~~y soft-
forms data format conversions between binary real data
ware when the MC68882 is used as a perl,~~:~~ktiith
any
formats to and from ‘the internal extended format. The
processor capable of memory-mapped
@+@yaTan M68000
CU relieves the APU of a significant work load and allows
style bus. When used as a periphe$$.@r@ssor
with the
the MC68882 to execute data movement and preparation
8-bit MC68008, the 16-bit MC68,R{:~$r?he
.MC68010, all
functions concurrently
with arithmetic and transcenden-
MC68882 instructions are trapp~$:$
the main processor
tal calculations,
to an exception handler at g$$cut?~n time. Thus, the soft-
The eight 80-bit floating-point
data registers (FPO-FP7)
ware emulation of the c~~~~~$~or interface protocol can
and the 32-bit control, status, and instruction
address
be totally transparent%~~:t~&Wser. The MC68882 can pre-
registers (FPCR, FPSR and FPIAR) are located in the APU.
vide a performancetW~~.@
for MC68000-based
designs
In addition to these registers, the APU contains a high-
by changing the ‘T~%~@’*processors to the MC68020 or
speed 67-bit arithmetic
unit used for both mantissa and
MC68030. Th,~~pftMre
migrates without change to the
exponent calculations, a barrel shifter that can shift from
next gener&k$&#$eq uipment
using the MC68020
or
1 bit to 67 bits
in one machine cycle, and ROM
constants
MC6803@s”’:?JW’
(for use by the internal algorithms
or user programs).
Sin@’J%&$s
is asynchronous,
the MC68882 need not
The control section of the APU contains the clock gen-
ru~.at~g
same clock speed as the main processor. Total
erator, a two-level microcode sequencer, the microcode
,J,~$&~~mperformance
may therefore be customized. For a
: Weti CPU performance
requirement,
the floating-point
ROM, and self-test circuitry. The built-in self-test capa-
bilities of the MC68882 enhance reliability and ease man- S+~&.$@’iformance can be selected to meet Particular Price/
ufacturing
requirements;
however,
these diagnost~~~%k~ performance
specifications,
running
the MC68882 at
functions are not accessible outside of the special test ‘t
slower (or faster) clock speeds than the MPU clock.
COPROCESSOR INTERFACE
Freescale Semiconductor, Inc...
,,
s~i;,y+,.>~.
All communications
between the MC68@~~OFWC68030
and the MC68882 occur via standard M@~~Q:@>amily bus
The MC68882 is design,~t~~~~~erate
on 8-,
transfers,
:f},\,.*7.
~:
>~$iy,
.\\<..
16-, or 32-bit data buses.
p?
The MC68882 contains a nu@b#~.~coprocessor
inter-
face registers (CIRS) that ar~.~~r$ised
in the same man-
ner as memory by the rnai~~~~essor.
The M68000 Family
coprocessor
interface.r$<!#~@emented
via a protocol of
reading and writing t$$~#se registers by the main pro-
cessor. The MC6@:~0 anfl MC68030 implement this gen-
~’.:!$ ..+
‘ ,~~
eral purpose co~ra$~ssor interface protocol in hardware
and microc~$~,$~~~ ~
WhenJh*~$~&68020 or MC68030 detects a general type
MC68&Q~~~s?tuction,
the MC68020 or MC68030 writes
the,i@tru$~on
to the memory-mapped
command CIR and
r~S&%l~&response
CIR. In this response, the BIU encodes
‘+’:t
.:.:.~’:~’.t~.
~i%{e$~ests for any additional action required of the MC68020
“$.@~C68030 on behalf of the MC68882. For example, the
‘%sponse may request that the MC68020 or MC68030 fetch
an operand from the evaluated effective address and
transfer
the operand
to the operand
CIR. Once the
MC68020 or MC68030 fulfills the coprocessor request(s),
the MC68020 or MC68030 is free to fetch and execute
subsequent instructions.
The only difference between a coprocessor bus transfer
and any other bus transfer is that the MC68020 or MC68030
issues a CPU address space function code during the
The M68000 Family coprocessor interface is an integral
part of the MC68882 and MC68020 or MC68030 designs.
The interface partitions MPU and coprocessor operations
so that the MC68020 or MC68030 does not have to corn-
pletely decode coprocessor instructions, and the MC68882
does not have to duplicate main processor functions (such
as effective address evaluation).
This partitioning
pro-
vides an orthogonal
extension of the instruction
set by
permitting
MC68882 instructions
to utilize all MC68020
or MC68030 addressing modes and to generate execution
time exception traps. Thus, from the programmer’s
view,
the MPU and coprocessor appear to be integrated onto
a single chip.
While the execution of the great majority of MC68882
instructions
may be overlapped
with the execution of
MC68020 or MC68030 instructions,
concurrency is com-
pletelytransparent
to the programmer. The MC68020 and
MC68030 single-step and program flow (trace) modes are
fully supported by the MC68882 and the M68000 Family
coprocessor interface.
While the M68000 Family coprocessor
interface per-
mits coprocessor
to be bus masters, the MC68882 is
never a bus master. The MC68882 requests that the
MC68020 or MC68030 fetch all operands and store all
results. In this manner, the MC68020 and MC68030 32-
bit data bus provides high speed transfer of floating-point
operands and results while simplifying
the design of the
MC68882.
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