Data Sheet
FEATURES
Delivers true rms or average rectified value of ac waveform
Fast settling at all input levels
Accuracy: ±10 μV ± 0.25% of reading (B grade)
Wide dynamic input range
100 μV rms to 3 V rms (8.5 V p-p) full-scale input range
Larger inputs with external scaling
Wide bandwidth:
1 MHz for −3 dB (300 mV)
65 kHz for additional 1% error
Zero converter dc output offset
No residual switching products
Specified at 300 mV rms input
Accurate conversion with crest factors up to 10
Low power: 300
µA
typical at ±2.4 V
High-Z FET separately powered input buffer
R
IN
≥ 10
12
Ω, C
IN
≤ 2 pF
Precision dc output buffer
Wide power supply voltage range
Dual: ±2.4 V to ±18 V; single: 4.8 V to 36 V
4 mm × 4 mm LFCSP and 8 mm × 6 mm QSOP packages
ESD protected
Low Cost, Low Power,
True RMS-to-DC Converter
AD8436
FUNCTIONAL BLOCK DIAGRAM
CAVG CCF
AD8436
SUM
RMS
8kΩ
RMS CORE
VCC
100kΩ
IGND
100kΩ
VEE
16kΩ
10pF
OGND
OUT
IBUFGN
IBUFIN–
IBUFIN+
10kΩ
–
10kΩ
IBUFOUT
+
FET OP AMP
OBUFIN+
OBUFIN–
16kΩ
+
–
DC BUFFER
Figure 1.
GENERAL DESCRIPTION
The
AD8436
is a new generation, translinear precision, low
power, true rms-to-dc converter loaded with options. It computes a
precise dc equivalent of the rms value of ac waveforms, including
complex patterns such as those generated by switch mode power
supplies and triacs. Its accuracy spans a wide range of input levels
(see Figure 2) and temperatures. The ensured accuracy of ≤±0.5%
and ≤10 μV output offset result from the latest Analog Devices,
Inc., technology. The crest factor error is <0.5% for CF values
between 1 and 10.
The
AD8436
delivers true rms results at less cost than misleading
peak, averaging, or digital solutions. There is no programming
expense or processor overhead to consider, and the 4 mm
4 mm
package easily fits into tight applications. On-board buffer
amplifiers enable the widest range of options for any rms-to-dc
converter available, regardless of cost. For minimal applications,
only a single external averaging capacitor is required. The built-in
high impedance FET buffer provides an interface for external
attenuators, frequency compensation, or driving low impedance
loads. A matched pair of internal resistors enables an easily
configurable gain-of-two or more, extending the usable input
range even lower. The low power, precision input buffer makes
the
AD8436
attractive for use in portable multi-meters and
other battery-powered applications.
Rev. E
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Trademarks and registered trademarks are the property of their respective owners.
The precision dc output buffer minimizes errors when driving
low impedance loads with extremely low offset voltages, thanks
to internal bias current cancellation. Unlike digital solutions, the
AD8436
has no switching circuitry limiting performance at high or
low amplitudes (see Figure 2). A usable response of <100 μV
and >3 V extends the dynamic range with no external scaling,
accommodating demanding low level signal conditions and
allowing ample overrange without clipping.
GREATER INPUT DYNAMIC RANGE
AD8436
∆Σ
SOLUTION
100µV
1mV
10mV
100mV
1V
3V
10033-002
Figure 2. Usable Dynamic Range of the
AD8436
vs. ΔΣ
The
AD8436
operates from single or dual supplies of ±2.4 V
(4.8 V) to ±18 V (36 V). A and J grades are available in a compact
4 mm × 4 mm, 20-lead chip-scale package; A and B grades are
available in a 20-lead QSOP package. The operating temperature
ranges are −40°C to 125°C for A and B grades and 0°C to 70°C
for J grade.
10033-001
OBUFOUT
AD8436
TABLE OF CONTENTS
Features .............................................................................................. 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
ESD Caution .................................................................................. 4
Pin Configurations and Function Descriptions ........................... 5
Typical Performance Characteristics ............................................. 6
Test Circuits ....................................................................................... 9
Data Sheet
Theory of Operation ...................................................................... 10
Overview ..................................................................................... 10
Applications Information .............................................................. 12
Using the AD8436 ...................................................................... 12
Additional Information ............................................................. 15
AD8436 Evaluation Board ............................................................ 17
Outline Dimensions ....................................................................... 20
Ordering Guide .......................................................................... 21
REVISION HISTORY
3/2017—Rev. D to Rev. E
Changed CP-20-10 to CP-20-8 .................................... Throughout
Changes to Outline Dimensions................................................... 21
Changes to Ordering Guide .......................................................... 22
10/2015—Rev. C to Rev. D
Changes to Figure 5 to Figure 8 ...................................................... 6
7/2015—Rev. B to Rev. C
Changes to Table 2 ............................................................................ 4
Changes to Figure 5 to Figure 7 ...................................................... 6
Changes to Figure 21 ........................................................................ 9
Changes to Using the FET Input Buffer Section ........................ 14
Changes to Single-Supply Section and Figure 39 ....................... 15
Added Additional Information Section....................................... 15
Changes to AD8436 Evaluation Board Section and A Word
About Using the AD8436 Evaluation Board Section ................... 17
Added Single-Supply Operation Section ..................................... 17
Changes to Ordering Guide .......................................................... 21
1/2013—Rev. A to Rev. B
Added B Grade Throughout ............................................. Universal
Changes to Figure 1 and changes to General Description .......... 1
Changes to Table 1 ............................................................................ 3
Changes to Figure 3 ......................................................................... 5
Changes to Figure 9 and Figure 10 ................................................. 6
Changes to FET Input Buffer Section .......................................... 11
Changes to Averaging Capacitor Considerations—RMS
Accuracy Section and changes to Figure 28 ................................ 12
Deleted Capacitor Construction Section; added CAVG
Capacitor Styles Section................................................................. 13
Added Converting to Average Rectified Value Section ............. 15
Changes to Figure 41 ...................................................................... 16
Changes to Evaluation Board Section .......................................... 17
Changes to Figure 48 ...................................................................... 19
Changes to Outline Dimensions................................................... 20
Changes to Ordering Guide .......................................................... 21
7/2012—Rev. 0 to Rev. A
Added 20-Lead QSOP ....................................................... Universal
Changes to Features Section and General Description Section ..1
Changes to Table 1.............................................................................3
Changes to Table 2.............................................................................4
Changes to Table 3 and added Figure 4 and added Table 4;
Renumbered Sequentially ................................................................5
Changes to Equation 1 and change to Column One Heading
in Table 5.......................................................................................... 10
Changes to Averaging Capacitor Considerations—RMS
Accuracy and to Post Conversion Ripple Reduction Filter
and changes to Figure 27 Caption ................................................ 12
Changes to Figure 30 to Figure 32................................................ 13
Changes to Using the FET Input Buffer Section and Using the
Output Buffer Section .................................................................... 14
Changes to Figure 38 and Figure 41 and added Converting
to Rectified Average Value Section .............................................. 15
Changes to Figure 41...................................................................... 16
Changes to Figure 42 to Figure 46................................................ 17
Changes to Figure 47 and Figure 48............................................. 18
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 20
7/2011—Revision 0: Initial Version
Rev. E | Page 2 of 21
Data Sheet
SPECIFICATIONS
AD8436
e
IN
= 300 mV (rms), frequency = 1 kHz sinusoidal, ac-coupled, ±V
S
= ±5 V, T
A
= 25°C, C
AVG
= 10 μF, unless otherwise specified.
Table 1.
Parameter
RMS CORE
Conversion Error
Vs. Temperature
Vs. Rail Voltage
Input V
OS
Output V
OS
Vs. Temperature
DC Reversal Error
Nonlinearity
Crest Factor Error
1 < CF < 10
Peak Input Voltage
Input Resistance
Response
1% Error
3 dB Bandwidth
Settling Time
0.1%
0.01%
Output Resistance
Supply Current
INPUT BUFFER
Voltage Swing
Input
Output
Offset Voltage
Input Bias Current
Input Resistance
Response
0.1 dB
3 dB Bandwidth
Supply Current
Optional Gain Resistor
Gain Error
OUTPUT BUFFER
Offset Voltage
Input Current (I
B
)
Output Swing
Output Drive Current
Gain Error
Supply Current
SUPPLY VOLTAGE
Dual
Single
1
Test Conditions/Comments
Default conditions
−40°C < T < 125 C
±2.4 V to ±18 V
DC-coupled
AC-coupled input
−40 C < T < 125°C
DC-coupled, V
IN
= ±300 mV
e
IN
= 2 mV to 500 mV ac
(Additional)
CCF = 0.1 μF
AD8436A, AD8436J
Min
Typ
Max
±10 − 0.5
±0 ± 0
0.006
±0.013
0
0
0.3
0
±0.2
±10 + 0.5
Min
±10 − 0.25
AD8436B
Typ
±0 ± 0
0.006
±0.013
0
0
0.3
0
±0.2
Max
±10 + 0.25
Unit
μV/% rdg
%/°C
±%/V
μV
V
μV/°C
%
%
%
V
kΩ
kHz
MHz
ms
ms
kΩ
μA
−500
+500
−250
+250
−1.5
+1.5
−1.0
+1.0
−0.5
−V
S
− 0.7
7.92
8
65
1
148/341
158/350
16
325
+0.5
+V
S
+ 0.7
8.08
−0.5
−V
S
− 0.7
7.92
8
65
1
148/341
158/350
16
325
+0.5
+V
S
+ 0.7
8.08
V
IN
= 300 mV rms
(Additional)
Rising/falling
Rising/falling
15.68
No input
G=1
AC- or dc-coupled
AC-coupled to Pin RMS
16.32
365
15.68
16.32
365
−V
S
−V
S
+ 0.2
−1
0
10
12
+V
S
+V
S
− 0.2
+1
50
−V
S
−V
S
+ 0.2
−0.5
0
10
12
950
2.1
160
+10
+V
S
+V
S
− 0.2
+0.5
50
V
mV
mV
pA
Ω
kHz
MHz
μA
kΩ
%
μV
nA
V
mA
%
μA
V
V
(Frequency)
950
2.1
160
+10
100
−9.9
G = ×1
R
L
=
Connected to Pin OUT
(Voltage)
−200
−V
S
+ 50e
−6
−0.5 (sink)
0.003
200
+10.1
0.05
+200
5
1
+V
S
− 1
+15 (source)
70
±18
36
100
−9.9
200
+10.1
0.05
+150
5
1
+V
S
− 1
+15 (source)
70
±18
36
0
2
−150
−V
S
+ 50e
−6
−0.5 (sink)
0.003
0
2
0.01
40
0.01
40
±2.4
4.8
±2.4
4.8
I
B
max measured at power up. Settles to typical value in <15 seconds.
Rev. E | Page 3 of 21
AD8436
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Voltage
Supply Voltage
Input Voltage Range
1
Differential Input
Current
Input Current
1
Output Short-Circuit Duration
Power Dissipation
CP-20-8 LFCSP Without Thermal Pad
CP-20-8 LFCSP With Thermal Pad
RQ Package
Temperature
Operating Range
Storage Range
Lead Soldering (60 sec)
θ
JA
2
CP-20-8 LFCSP Without Thermal Pad
CP-20-8 LFCSP With Thermal Pad
RQ-20 Package
ESD Rating
1
Data Sheet
Rating
±18 V
VEE − 0.3 V to VCC + 0.3 V
VCC and VEE
±10 mA
Indefinite
1.2 W
2.1 W
1.1 W
−40°C to +125°C
−65°C to +125°C
300°C
86°C/W
48°C/W
95°C/W
2 kV
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Input pins have clamp diodes to the power supply pins. Limit input current
to 10 mA or less whenever input signals exceed the power supply rail by 0.3 V.
2
θ
JA
is specified for the worst-case conditions, that is, a device soldered in a circuit
board for surface-mount packages.
Rev. E | Page 4 of 21
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
SUM
20
1
DNC
PIN 1
INDICATOR
CAVG
CCF
VCC
IBUFV+
16
15
OBUFV+
AD8436
SUM
1
DNC
2
RMS
3
IBUFOUT
4
20
CAVG
19
CCF
18
VCC
AD8436
TOP VIEW
(Not to Scale)
17
IBUFV+
16
OBUFV+
15
OBUFOUT
14
OBUFIN–
13
OBUFIN+
12
IGND
11
VEE
10033-104
RMS
OBUFOUT
IBUFIN–
5
IBUFIN+
6
IBUFGN
7
AD8436
IBUFOUT
TOP VIEW
(Not to Scale)
OBUFIN–
DNC
8
OGND
9
IBUFIN–
OBUFIN+
OUT
10
IBUFIN+
5
6
IBUFGN
DNC
OGND
OUT
VEE
10
11
IGND
NOTES
1. DNC = DO NOT CONNECT.
DO NOT CONNECT TO THIS PIN.
Figure 3. Pin Configuration, Top View, CP-20-8
10033-003
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED PAD CONNECTION IS OPTIONAL.
Figure 4. Pin Configuration, RQ-20
Table 3. Pin Function Descriptions, CP-20-8
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
EP
Mnemonic
DNC
RMS
IBUFOUT
IBUFIN−
IBUFIN+
IBUFGN
DNC
OGND
OUT
VEE
IGND
OBUFIN+
OBUFIN−
OBUFOUT
OBUFV+
IBUFV+
VCC
CCF
CAVG
SUM
DNC
Description
Do Not Connect. Used for factory test.
AC Input to the RMS Core.
FET Input Buffer Output Pin.
FET Input Buffer Inverting Input Pin.
FET Input Buffer Noninverting Input Pin.
Optional 10 kΩ Precision Gain Resistor.
Do Not Connect. Used for factory test.
Internal 16 kΩ I-to-V Resistor.
RMS Core Voltage or Current Output.
Negative Supply Rail.
Half Supply Node.
Output Buffer Noninverting Input Pin.
Output Buffer Inverting Input Pin.
Output Buffer Output Pin.
Power Pin for the Output Buffer.
Power Pin for the Input Buffer.
Positive Supply Rail for the RMS Core.
Connection for Crest Factor Capacitor.
Connection for Averaging Capacitor.
Summing Amplifier Input Pin.
Exposed Pad Connection to Ground
Pad Optional.
Table 4. Pin Function Descriptions, RQ-20
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Mnemonic
SUM
DNC
RMS
IBUFOUT
IBUFIN−
IBUFIN+
IBUFGN
DNC
OGND
OUT
VEE
IGND
OBUFIN+
OBUFIN−
OBUFOUT
OBUFV+
IBUFV+
VCC
CCF
CAVG
Description
Summing Amplifier Input Pin.
Do Not Connect. Used for factory test.
AC Input to the RMS Core.
FET Input Buffer Output Pin.
FET Input Buffer Inverting Input Pin.
FET Input Buffer Noninverting Input Pin.
Optional 10 kΩ Precision Gain Resistor.
Do Not Connect. Used for factory test.
Internal 16 kΩ I-to-V Resistor.
RMS Core Voltage or Current Output.
Negative Supply Rail.
Half Supply Node.
Output Buffer Noninverting Input Pin.
Output Buffer Inverting Input Pin.
Output Buffer Output Pin.
Power Pin for the Output Buffer.
Power Pin for the Input Buffer.
Positive Supply Rail for the RMS Core.
Connection for Crest Factor Capacitor.
Connection for Averaging Capacitor.
Rev. E | Page 5 of 21
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