Operating Temperature Range...............................0°C to +85°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
DD
= +10V, V
SS
= -4V, V
LOGIC
= V
LDAC
= V
LSHA
= +5V, V
REF
= +2.5V, V
AGND
= V
DGND
= V
GS
= 0V, R
L
≥
10MΩ, C
L
= 50pF,
CLKSEL = +5V, f
ECLK
= 400kHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
DC CHARACTERISTICS
Resolution
Output Range
Offset Voltage
Offset Voltage Tempco
Gain Error
Gain Tempco
Integral Linearity Error
Differential Linearity Error
Maximum Output Drive Current
DC Output Impedance
INL
DNL
I
OUT
R
OUT
V
OUT_
= -3.25V to +7.6V
V
OUT_
= -3.25V to +7.6V. Monotonicity
guaranteed to 14 bits
Sinking and sourcing
MAX5631
MAX5632
MAX5633
MAX5631
Maximum Capacitive Load
DC Crosstalk
Power-Supply Rejection Ratio
PSRR
MAX5632
MAX5633
Internal oscillator enabled (Note 3)
Internal oscillator enabled
±2
35
350
700
50
500
1000
250
10
10
-90
-80
65
650
1300
pF
nF
dB
dB
Ω
(Note 2)
±5
0.005
±1
0.015
±4
N
V
OUT_
(Note 1)
Code = 4F2C hex
16
V
SS
+
0.75
±15
±50
±1
V
DD
-
2.4
±200
Bits
V
mV
µV/°C
%
ppm/°C
%FSR
LSB
mA
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
Maxim Integrated
MAX5631/MAX5632/MAX5633
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +10V, V
SS
= -4V, V
LOGIC
= V
LDAC
= V
LSHA
= +5V, V
REF
= +2.5V, V
AGND
= V
DGND
= V
GS
= 0V, R
L
≥
10MΩ, C
L
= 50pF,
CLKSEL = +5V, f
ECLK
= 400kHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
DYNAMIC CHARACTERISTICS
Sample-and-Hold Settling
SCLK Feedthrough
f
SEQ
Feedthrough
Hold-Step
Droop Rate
Output Noise
REFERENCE INPUT
Input Resistance
Reference Input Voltage
GROUND-SENSE INPUT
Input Voltage Range
Input Bias Current
GS Gain
Input High Voltage
Input Low Voltage
Input Current
TIMING CHARACTERISTICS
(FIGURE 2)
Sequencer Clock Frequency
External Clock Frequency
SCLK Frequency
SCLK Pulse Width High
SCLK Pulse Width Low
CS
Low to SCLK High Setup
Time
CS
High to SCLK High Setup
Time
SCLK High to
CS
Low Hold Time
f
SEQ
f
ECLK
f
SCLK
t
CH
t
CL
t
CSSO
t
CSS1
t
CSH0
15
15
15
15
10
Internal oscillator
(Note 7)
80
100
120
480
20
kHz
kHz
MHz
ns
ns
ns
ns
ns
V
IH
V
IL
V
GS
I
GS
-0.5V
≤
V
GS
≤
0.5V
(Note 6)
-0.5
-60
0.998
2.0
0.8
±1
1
0.5
0
1.002
V
µA
V/V
V
V
µA
V
REF
7
2.5
kΩ
V
V
OUT_
= 0V (Note 5), T
A
= +25°C
(Note 4)
0.5
0.5
0.25
1
250
1
40
0.08
%
nV-s
nV-s
mV
mV/s
µV
RMS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INTERFACE DC CHARACTERISTICS
Maxim Integrated
3
MAX5631/MAX5632/MAX5633
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +10V, V
SS
= -4V, V
LOGIC
= V
LDAC
= V
LSHA
= +5V, V
REF
= +2.5V, V
AGND
= V
DGND
= V
GS
= 0V, R
L
≥
10MΩ, C
L
= 50pF,
CLKSEL = +5V, f
ECLK
= 400kHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
SCLK High to
CS
High Hold Time
DIN to SCLK High Setup Time
DIN to SCLK High Hold Time
RST
to
CS
Low
POWER SUPPLIES
Positive Supply Voltage
Negative Supply Voltage
Supply Difference
Logic Supply Voltage
Positive Supply Current
Negative Supply Current
Logic Supply Current
V
LOGIC
,
V
LDAC
,
V
LSHA
I
DD
I
SS
I
LOGIC
(Note 10)
f
SCLK
= 20MHz (Note 11)
V
DD
V
SS
(Note 9)
(Note 9)
V
DD
- V
SS
(Note 9)
4.75
5
32
32
1
2
8.55
-5.25
10
-4
11.6
-2.75
14.5
5.25
42
40
1.5
3
V
V
V
V
mA
mA
mA
SYMBOL
t
CSH1
t
DS
t
DH
(Note 8)
CONDITIONS
MIN
0
15
0
500
TYP
MAX
UNITS
ns
ns
ns
µs
Note 1:
The nominal zero-scale (code = 0) voltage is -4.0535V. The nominal full-scale (code = FFFF hex) voltage is +9.0535V. The
output voltage is limited by the Output Range specification, restricting the useable range of DAC codes. The nominal zero-
scale voltage may be achieved when V
SS
< -4.9V, and the nominal full-scale voltage may be achieved when V
DD
> +11.5V.
Note 2:
Gain is calculated from measurements
for voltages V
DD
= 10V and V
SS
= -4V at codes C000 hex and 4F2C hex,
for voltages V
DD
= 11.6V and V
SS
= -2.9V at codes FFFF hex and 252E hex,
for voltages V
DD
= 9.25V and V
SS
= -5.25V at codes D4F6 hex and 0 hex, and
for voltages V
DD
= 8.55V and V
SS
= -2.75V at codes C74A hex and 281C hex.
Note 3:
Steady-state change in any output with an 8V change in an adjacent output.
Note 4:
Settling during the first update for an 8V step. The output will settle to within the linearity specification on subsequent
updates. Tested with an external sequencer clock frequency of 480kHz.
Note 5:
External clock mode with the external clock not toggling.
Note 6:
The output voltage is the sum of the DAC output and the voltage at GS. GS gain is measured at 4F2C hex.
Note 7:
The sequencer runs at f
SEQ
= f
ECLK
/4. Maximum speed is limited by settling of the DAC and SHAs. Minimum speed is
limited by acceptable droop and update time after a Burst Mode Update.
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stm32/stm8
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