Programmable FemtoClock
®
LVPECL
Oscillator Replacement
83PR226I-01
Datasheet
Description
The 83PR226I-01 is a programmable LVPECL synthesizer that is
“forward” footprint compatible with standard 5mm x 7mm oscillators.
Forward footprint compatibility means, a board is designed to
accommodate the crystal oscillator interface, and the optional
control pins are also fully compatible with a canned oscillator
footprint (the canned oscillator will drop onto the 10-VFQFN footprint
for second sourcing purposes). This capability provides designers
with programability and lead time advantages of silicon/crystal based
solutions, while maintaining compatibility with industry standard
5mm x 7mm oscillator footprints for ease of supply chain
management. Oscillator-level performance is maintained with IDT’s
3
rd
generation FemtoClock
®
PLL technology, which delivers sub 1ps
RMS phase jitter.
The 83PR226I-01 defaults to 125MHz using a 25MHz crystal with all
4 of the programming pins floating (pulled HIGH with internal pullup
resistors), but can be also be set to 15 different frequency multiplier
settings to support a wide variety of applications. The table below
shows some of the more common application settings.
Features
•
•
•
•
•
•
•
•
•
•
•
•
Footprint compatible with 5mm x 7mm differential oscillators
One differential LVPECL output pair
Crystal oscillator interface which can also be overdriven a
single-ended or differential reference clock
Output frequency range: 83.33MHz – 213.33MHz
Crystal/Input frequency range: 15.625MHz – 32MHz
VCO range: 500MHz – 640MHz
PCI Express (2.5Gb/s) and Gen 2 (5 Gb/s) jitter compliant
Cycle-to-cycle jitter: 45ps (maximum)
RMS phase jitter @ 125MHz, 1.875MHz – 20MHz:
0.47ps (typical)
Full 3.3V or 2.5V operating supply
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) packages
Common Applications and Settings (not exhaustive)
M1
0
0
0
0
0
1
1
1
1
1
1
M0
0
0
0
1
1
0
1
1
1
1
1
N1
1
1
1
0
0
0
0
0
0
1
1
N0
0
0
1
0
1
1
0
1
1
0
1
XTAL
(MHz)
19.44
19.2
19.2
26.5625
26.5625
25
24
24
22.5
25
25
Output Freq
(MHz)
Application(s)
155.52
153.6
122.8
106.25
212.5
166.66
100
200
187.5
156.25
125
SONET
N0
N1
Pin Assignments
10
9
W-CDMA
W-CDMA
1G, 2G Fibre Channel
M0
M1
1
8
V
CC
2G, 4G Fibre Channel
Processor, PCI-X
Processor, PCI Express 1
Processor, PCI Express 2
12G Ethernet
10 Gb Ethernet
1 Gb Ethernet (default)
V
EE
2
7
nQ
3
4
XTAL_IN
5
XTAL_OUT
6
Q
83PR226I-01
10-VFQFN
5mm x 7mm x 1mm package body
K Package
Top View
©2017 Integrated Device Technology, Inc.
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April 13, 2017
83PR226I-01 Datasheet
Block Diagram
N0
N1
Pullup
Pullup
XTAL_IN
OSC
Phase Detector
FemtoClock VCO
500MHz – 640MHz
XTAL_OUT
Output Divider
N[1:0] Value
00
÷6
01
÷3
10
÷4
11
÷5 (default)
Q
nQ
M1 M0
0
0
0
1
1
0
1
1
M Value
÷32
÷24
÷20
÷25 (default)
M1
M0
Pullup
Pullup
Table 1. Pin Descriptions
Number
1, 2
3
4, 5
6, 7
8
9, 10
Name
M1, M0
V
EE
XTAL_IN
XTAL_OUT
Q, nQ
V
CC
N1, N0
Input
Power
Input
Output
Power
Input
Pullup
Type
Pullup
Description
Feedback divider control inputs. Sets the feedback divider value to one of four
values: ÷32, ÷25, ÷24, or ÷20 (see Table 3A). LVCMOS/LVTTL interface levels.
Negative supply pin.
Crystal oscillator interface XTAL_IN is the input, XTAL_OUT is the output. This
oscillator interface can also be driven by a single-ended or differential reference
clock.
Differential output pair. LVPECL interface levels.
Power supply pin.
Output divider control inputs. Sets the output divider value to one of four values:
÷3, ÷4, ÷5, or ÷6 (see Table 3B). LVCMOS/LVTTL interface levels.
NOTE:
Pullup
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
Parameter
Input Capacitance
Input Pullup Resistor
Test Conditions
Minimum
Typical
3.5
51
Maximum
Units
pF
k
©2017 Integrated Device Technology, Inc.
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83PR226I-01 Datasheet
Function Tables
Table 3A. Feedback Divider M Function Table
M1
0
0
1
1
M0
0
1
0
1
M Value
÷32
÷24
÷20
÷25
Table 3B. Output Divider N Function Table
N1
0
0
1
1
N0
0
1
0
1
M Value
÷6
÷3
÷4
÷5
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
38.05C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
CC
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
172
Units
V
mA
©2017 Integrated Device Technology, Inc.
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83PR226I-01 Datasheet
Table 4B. Power Supply DC Characteristics,
V
CC
= 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
150
Units
V
mA
Table 4C. LVCMOS/LVTTL DC Characteristics,
V
CC
= 3.3V ± 5% or 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
IH
Parameter
Input High Voltage
Test Conditions
V
CC
= 3.465V
V
CC
= 2.625V
Input Low Voltage
Input High Current
Input Low Current
M[1:0], N[1:0]
M[1:0], N[1:0]
V
CC
= 3.465V
V
CC
= 2.625V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
-150
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
CC
+ 0.3
V
CC
+ 0.3
0.8
0.7
5
Units
V
V
V
V
µA
µA
V
IL
I
IH
I
IL
Table 4D. LVPECL DC Characteristics,
V
CC
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CC
– 1.4
V
CC
– 2.0
0.6
Typical
Maximum
V
CC
– 0.9
V
CC
– 1.7
1.0
Units
V
V
V
NOTE 1: Outputs termination with 50 to V
CC
– 2V.
Table 4E. LVPECL DC Characteristics,
V
CC
= 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CC
– 1.4
V
CC
– 2.0
0.4
Typical
Maximum
V
CC
– 0.9
V
CC
– 1.5
1.0
Units
V
V
V
NOTE 1: Outputs termination with 50 to V
CC
– 2V.
Table 5. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
15.625
Test Conditions
Minimum
Typical
Fundamental
32
50
7
MHz
Maximum
Units
pF
©2017 Integrated Device Technology, Inc.
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83PR226I-01 Datasheet
AC Electrical Characteristics
Table 6A. AC Characteristics,
V
CC
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
f
MAX
tjit(cc)
Parameter
Output Frequency
Cycle-to-Cycle Jitter;
NOTE 1
156.25MHz,
Integration Range: 1.875MHz – 20MHz
tjit(Ø)
RMS Phase Jitter
(Random);
NOTE 2
125MHz,
Integration Range: 1.875MHz – 20MHz
100MHz,
Integration Range: 1.875MHz – 20MHz
100MHz, (1.2MHz – 21.9MHz),
10
6
samples,
25MHz crystal input
125MHz, (1.2MHz – 21.9MHz),
10
6
samples,
25MHz crystal input
100MHz, 25MHz crystal input
125MHz, 25MHz crystal input
20% to 80%
200
47
0.44
0.47
0.48
Test Conditions
Minimum
83.33
Typical
Maximum
213.33
45
Units
MHz
ps
ps
ps
ps
t
j
(PCIe Gen 1)
Phase Jitter
Peak-to-Peak;
NOTE 3
17.20
ps
16.52
1.70
1.61
700
53
100
ps
ps
ps
ps
%
ms
t
REFCLK_HF_RMS
(PCIe Gen 2)
t
R
/ t
F
odc
t
LOCK
Phase Jitter RMS;
NOTE 4
Output Rise/Fall Time
Output Duty Cycle
PLL Lock Time;
NOTE 5
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Please refer to the Phase Noise plots.
NOTE 3: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express
Gen 1 is 86ps peak-to-peak for a sample size of 10
6
clock periods.
NOTE 4: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and
reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for t
REFCLK_HF_RMS
(High Band) and 3.0ps RMS for t
REFCLK_LF_RMS
(Low Band).
NOTE 5: This parameter is guaranteed using a 25MHz crystal.
©2017 Integrated Device Technology, Inc.
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April 13, 2017
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