Am29F016D
Data Sheet
Am29F016D Cover Sheet
The following document contains information on Spansion memory products.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been
made are the result of normal data sheet improvement and are noted in the document revision summary.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
Publication Number
21444
Revision
E
Amendment
9
Issue Date
November 16, 2009
D at a
S hee t
This page left intentionally blank.
2
Am29F016D
21444_E9 November 16, 2009
DATA SHEET
Am29F016D
16 Megabit (2 M x 8-Bit)
CMOS 5.0 Volt-only, Uniform Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■
5.0 V
±
10%, single power supply operation
— Minimizes system level power requirements
■
Manufactured on 0.23 µm process technology
— Compatible with 0.5 µm Am29F016 and 0.32 µm
Am29F016B devices
■
High performance
— Access times as fast as 70 ns
■
Low power consumption
— 25 mA typical active read current
— 30 mA typical program/erase current
— 1 µA typical standby current (standard access
time to active mode)
■
Flexible sector architecture
— 32 uniform sectors of 64 Kbytes each
— Any combination of sectors can be erased
— Supports full chip erase
— Group sector protection:
A hardware method of locking sector groups to
prevent any program or erase operations within
that sector group
Temporary Sector Group Unprotect allows code
changes in previously locked sectors
■
Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies bytes at specified addresses
■
Unlock Bypass Program Command
— Reduces overall programming time when
issuing multiple program command sequences
■
Minimum 1,000,000 program/erase cycles per
sector guaranteed
■
20-year data retention at 125° C
— Reliable operation for the life of the system
■
Package options
— 48-pin and 40-pin TSOP
— 44-pin SO
— Known Good Die (KGD)
(see publication number 21551)
■
Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply Flash standard
— Superior inadvertent write protection
■
Data# Polling and toggle bits
— Provides a software method of detecting
program or erase cycle completion
■
Ready/Busy# output (RY/BY#)
— Provides a hardware method for detecting
program or erase cycle completion
■
Erase Suspend/Erase Resume
— Suspends a sector erase operation to read data
from, or program data to, a non-erasing sector,
then resumes the erase operation
■
Hardware reset pin (RESET#)
— Resets internal state machine to the read mode
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication#
21444
Rev:
E
Amendment:
9
Issue Date:
November 16, 2009
D A T A
S H E E T
GENERAL DESCRIPTION
The Am29F016D is a 16 Mbit, 5.0 volt-only Flash mem-
ory organized as 2,097,152 bytes. The 8 bits of data
appear on DQ0–DQ7. The Am29F016D is offered in
48-pin TSOP, 40-pin TSOP, and 44-pin SO packages.
The device is also available in Known Good Die (KGD)
form. For more information, refer to publication number
21551. This device is designed to be programmed
in-system with the standard system 5.0 volt V
CC
supply.
A 12.0 volt V
PP
is not required for program or erase
operations. The device can also be programmed in
standard EPROM programmers.
This device is manufactured using AMD’s 0.23 µm pro-
cess technology, and offers all the features and
benefits of the Am29F016, which was manufactured
using 0.5 µm process technology.
The standard device offers access times of 70 and
90 ns, allowing high-speed microprocessors to operate
without wait states. To eliminate bus contention, the de-
vice has separate chip enable (CE#), write enable
(WE#), and output enable (OE#) controls.
The device requires only a
single 5.0 volt power sup-
ply
for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard.
Com-
mands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write cy-
cles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the
Embedded
Program
algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the
Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle)
status bits.
After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.
The
sector erase architecture
allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The
hardware sector
protection
feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved via programming equipment.
The
Erase Suspend
feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The
hardware RESET# pin
terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The system can place the device into the
standby
mode.
Power consumption is greatly reduced in
this mode.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.
2
Am29F016D
21444E9 November 16, 2009
D A T A
S H E E T
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . .
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Information . . . . . . . . . . . . . . . . . . . . . . .
Device Bus Operations . . . . . . . . . . . . . . . . . . . . .
Requirements for Reading Array Data .....................................
Writing Commands/Command Sequences ..............................
Program and Erase Operation Status ......................................
Standby Mode ..........................................................................
RESET#: Hardware Reset Pin .................................................
Output Disable Mode................................................................
4
4
5
6
6
7
8
8
8
9
9
9
9
DQ7: Data# Polling................................................................. 20
Figure 4. Data# Polling Algorithm ................................................. 20
Table 1. Am29F016D Device Bus Operations .................................. 8
RY/BY#: Ready/Busy#............................................................
DQ6: Toggle Bit I ....................................................................
DQ2: Toggle Bit II ...................................................................
Reading Toggle Bits DQ6/DQ2...............................................
DQ5: Exceeded Timing Limits ................................................
DQ3: Sector Erase Timer .......................................................
21
21
21
21
22
22
Figure 5. Toggle Bit Algorithm....................................................... 22
Table 10. Write Operation Status................................................... 23
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 24
Figure 6. Maximum Negative Overshoot Waveform ..................... 24
Figure 7. Maximum Positive Overshoot Waveform....................... 24
Table 2. Sector Address Table........................................................ 10
Autoselect Mode..................................................................... 11
Table 3. Am29F016D Autoselect Codes (High Voltage Method).... 11
Sector Group Protection/Unprotection.................................... 11
Table 4. Sector Group Addresses................................................... 11
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 24
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 25
TTL/NMOS Compatible .......................................................... 25
CMOS Compatible.................................................................. 25
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 8. Test Setup..................................................................... 26
Table 11. Test Specifications ......................................................... 26
Temporary Sector Group Unprotect ....................................... 11
Figure 1. Temporary Sector Group Unprotect Operation............... 12
Hardware Data Protection ...................................................... 12
Low V
CC
Write Inhibit ...................................................................... 12
Write Pulse “Glitch” Protection........................................................ 12
Logical Inhibit .................................................................................. 12
Power-Up Write Inhibit .................................................................... 12
Key to Switching Waveforms. . . . . . . . . . . . . . . . 26
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 27
Read-only Operations............................................................. 27
Figure 9. Read Operation Timings ................................................ 27
Figure 10. RESET# Timings ......................................................... 28
Erase/Program Operations..................................................... 29
Figure 11. Program Operation Timings.........................................
Figure 12. Chip/Sector Erase Operation Timings .........................
Figure 13. Data# Polling Timings (During Embedded Algorithms)
Figure 14. Toggle Bit Timings (During Embedded Algorithms).....
Figure 15. DQ2 vs. DQ6................................................................
Figure 16. Temporary Sector Group Unprotect Timings ...............
30
31
32
32
33
33
Common Flash Memory Interface (CFI) . . . . . . . 13
Table 5. CFI Query Identification String .......................................... 13
Table 6. System Interface String..................................................... 13
Table 7. Device Geometry Definition .............................................. 14
Table 8. Primary Vendor-Specific Extended Query ........................ 14
Command Definitions . . . . . . . . . . . . . . . . . . . . . 15
Reading Array Data ................................................................ 15
Reset Command..................................................................... 15
Autoselect Command Sequence ............................................ 15
Byte Program Command Sequence....................................... 15
Unlock Bypass Command Sequence.............................................. 16
Figure 2. Program Operation ......................................................... 16
Erase and Program Operations.............................................. 34
Alternate CE# Controlled Writes .................................................... 34
Figure 17. Alternate CE# Controlled Write Operation Timings ..... 35
Chip Erase Command Sequence ........................................... 16
Sector Erase Command Sequence ........................................ 17
Erase Suspend/Erase Resume Commands........................... 17
Figure 3. Erase Operation.............................................................. 18
Command Definitions ............................................................. 19
Table 9. Am29F016D Command Definitions................................... 19
Erase and Programming Performance . . . . . . . 36
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 36
TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 36
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 37
TS 040—40-Pin Standard Thin Small Outline Package ......... 37
TS 048—48-Pin Standard Thin Small Outline Package ......... 38
SO 044—44-Pin Small Outline Package ................................ 39
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 40
Write Operation Status . . . . . . . . . . . . . . . . . . . . 20
November 16, 2009 21444E9
Am29F016D
3
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