KSZ8851-32MQL datasheet, PDF - EEWORLD Datasheet

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KSZ8851-32MQL: DescriptionEthernet ICs 10/100BT Ethernet MAC + PHY with Generic (32-bit) Bus Interface (I-Temp); CategoryWireless rf/communication Telecom circuit; File Size673KB，90 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com; Environmental Compliance

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KSZ8851-32MQL Overview

Ethernet ICs 10/100BT Ethernet MAC + PHY with Generic (32-bit) Bus Interface (I-Temp)

KSZ8851-32MQL Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Microchip
package instruction	QFP-128
Reach Compliance Code	compliant
Factory Lead Time	17 weeks
JESD-30 code	R-PQFP-G128
JESD-609 code	e3
length	20 mm
Humidity sensitivity level	3
Number of functions	1
Number of terminals	128
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	FQFP
Package shape	RECTANGULAR
Package form	FLATPACK, FINE PITCH
Peak Reflow Temperature (Celsius)	245
Certification status	Not Qualified
Maximum seat height	3.4 mm
Nominal supply voltage	1.8 V
surface mount	YES
technology	CMOS
Telecom integrated circuit types	ETHERNET TRANSCEIVER
Temperature level	COMMERCIAL
Terminal surface	MATTE TIN
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	14 mm
Base Number Matches	1

User Manual

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KSZ8851-16/32MQL/MQLI

Single-Port Ethernet MAC Controller

with 8/16-Bit or 32-Bit Non-PCI Interface

Rev. 2.0

General Description

The KSZ8851M-series is a single-port controller chip with

a non-PCI CPU interface and is available in 8/16-bit and

32-bit bus designs. This datasheet describes the 128-pin

PQFP KSZ8851-16/32MQL for applications requiring high-

performance from single-port Ethernet Controller with

8/16-bit or 32-bit generic processor interface. The

KSZ8851M offers the most cost-effective solution for

adding high-throughput Ethernet connectivity to traditional

embedded systems.

The KSZ8851M is a single chip, mixed analog/digital

device offering Wake-on-LAN technology for effectively

addressing Fast Ethernet applications. It consists of a Fast

Ethernet MAC controller, an 8-bit, 16-bit and 32-bit generic

host processor interface and incorporates a unique

dynamic memory pointer with 4-byte buffer boundary and

a fully utilizable 18KB for both TX (allocated 6KB) and RX

(allocated 12KB) directions in host buffer interface.

The KSZ8851M is designed to be fully compliant with the

appropriate IEEE 802.3 standards. An industrial

temperature-grade version of the KSZ8851M, the

KSZ8851MQLI is also available (see “Ordering Information

section).

LinkMD

Physical signal transmission and reception are enhanced

through the use of analog circuitry, making the design

more efficient and allowing for lower-power consumption.

The KSZ8851M is designed using a low-power CMOS

process that features a single 3.3V power supply with

options for 1.8V, 2.5V or 3.3V VDD I/O. The device

includes an extensive feature set that offers management

information base (MIB) counters and CPU control/data

interfaces with single bus timing.

The KSZ8851M includes unique cable diagnostics feature

called LinkMD . This feature determines the length of the

cabling plant and also ascertains if there is an open or

short condition in the cable. Accompanying software

enables the cable length and cable conditions to be

conveniently displayed. In addition, the KSZ8851M

supports Hewlett Packard (HP) Auto-MDIX thereby

eliminating the need to differentiate between straight or

crossover cables in applications.

Functional Diagram

Figure 1. KSZ8851-16/32MQL/MQLI Functional Diagram

LinkMD is a registered trademark of Micrel, Inc.

Magic Packet is a trademark of Advanced Micro Devices, Inc.

Product names used in this datasheet are for identification purposes

only and may be trademarks of their respective companies.

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (

408

) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com

August 2009

M9999-083109-2.0

Micrel, Inc.

KSZ8851-16/32 MQL/MQLI

Contents

Pin Configuration for 16-Bit

............................................................................................................................................... 10

Pin Description for 16-Bit

................................................................................................................................................... 11

Pin Configuration for 32-Bit

............................................................................................................................................... 16

Pin Description for 32-Bit

................................................................................................................................................... 17

Strapping Options

............................................................................................................................................................... 21

Functional Description

....................................................................................................................................................... 22

Functional Overview

........................................................................................................................................................... 22

Power Management........................................................................................................................................................ 22

Normal Operation Mode ................................................................................................................................................. 22

Energy Detect Mode ....................................................................................................................................................... 22

Soft Power Down Mode .................................................................................................................................................. 23

Power Saving Mode........................................................................................................................................................ 23

Power Down ................................................................................................................................................................... 23

Wake-on-LAN.......................................................................................................................................................................

Detection of Energy ........................................................................................................................................................ 23

Detection of Linkup ......................................................................................................................................................... 24

Wake-up Packet ............................................................................................................................................................. 24

Magic Packet™............................................................................................................................................................... 24

Physical Layer Transceiver (PHY)

..................................................................................................................................... 24

100BASE-TX Transmit ................................................................................................................................................... 24

100BASE-TX Receive .................................................................................................................................................... 25

PLL Clock Synthesizer (Recovery)................................................................................................................................. 25

Scrambler/De-scrambler (100BASE-TX only) ................................................................................................................ 25

10BASE-T Transmit........................................................................................................................................................ 25

10BASE-T Receive......................................................................................................................................................... 25

MDI/MDI-X Auto Crossover ............................................................................................................................................ 25

Straight Cable

.......................................................................................................................................................... 26

Crossover Cable

...................................................................................................................................................... 26

Auto Negotiation ............................................................................................................................................................. 27

LinkMD Cable Diagnostics............................................................................................................................................ 28

Access...................................................................................................................................................................... 28

Usage ....................................................................................................................................................................... 28

Media Access Control (MAC) Operation

........................................................................................................................... 29

Inter Packet Gap (IPG) ................................................................................................................................................... 29

Back-Off Algorithm.......................................................................................................................................................... 29

Late Collision .................................................................................................................................................................. 29

Flow Control.................................................................................................................................................................... 29

Half-Duplex Backpressure.............................................................................................................................................. 29

Address Filtering Function .............................................................................................................................................. 30

Clock Generator.............................................................................................................................................................. 31

Bus Interface Unit (BIU)......................................................................................................................................................

Supported Transfers ....................................................................................................................................................... 31

Physical Data Bus Size .................................................................................................................................................. 31

Little and Big Endian Support ......................................................................................................................................... 32

Asynchronous Interface .................................................................................................................................................. 32

BIU Summation............................................................................................................................................................... 32

Queue Management Unit (QMU)

........................................................................................................................................ 33

August 2009

M9999-083109-2.0

Micrel, Inc.

KSZ8851-16/32 MQL/MQLI

Transmit Queue (TXQ) Frame Format ........................................................................................................................... 33

Frame Transmitting Path Operation in TXQ ................................................................................................................... 34

Driver Routine for Transmit Packet from Host Processor to KSZ8851M ....................................................................... 35

Receive Queue (RXQ) Frame Format............................................................................................................................ 38

Frame Receiving Path Operation in RXQ....................................................................................................................... 38

Driver Routine for Receive Packet from KSZ8851M to Host Processor ........................................................................ 39

EEPROM Interface...............................................................................................................................................................

Loopback Support........................................................................................................................................................... 41

Near-end (Remote) Loopback ........................................................................................................................................ 41

Far-end (Local) Loopback .............................................................................................................................................. 41

CPU Interface I/O Registers

............................................................................................................................................... 42

I/O Registers................................................................................................................................................................... 42

Internal I/O Registers Space Mapping............................................................................................................................ 43

Register Map: MAC, PHY and QMU...................................................................................................................................

Bit Type Definition........................................................................................................................................................... 49

0x00 – 0x05: Reserved................................................................................................................................................... 49

Bus Error Status Register (0x06 – 0x07): BESR............................................................................................................ 49

Chip Configuration Register (0x08 – 0x09): CCR .......................................................................................................... 49

0x0A – 0x0F: Reserved .................................................................................................................................................. 50

Host MAC Address Registers: MARL, MARM and MARH ............................................................................................. 50

Host MAC Address Register Low (0x10 – 0x11): MARL................................................................................................ 50

Host MAC Address Register Middle (0x12 – 0x13): MARM........................................................................................... 50

Host MAC Address Register High (0x14 – 0x15): MARH .............................................................................................. 50

0x16 – 0x1F: Reserved .................................................................................................................................................. 51

On-Chip Bus Control Register (0x20 – 0x21): OBCR .................................................................................................... 51

EEPROM Control Register (0x22 – 0x23): EEPCR ....................................................................................................... 51

Memory BIST Info Register (0x24 – 0x25): MBIR .......................................................................................................... 52

Global Reset Register (0x26 – 0x27): GRR ................................................................................................................... 52

0x28 – 0x29: Reserved................................................................................................................................................... 52

Wakeup Frame Control Register (0x2A – 0x2B): WFCR ............................................................................................... 52

0x2C – 0x2F: Reserved .................................................................................................................................................. 53

Wakeup Frame 0 CRC0 Register (0x30 – 0x31): WF0CRC0 ........................................................................................ 53

Wakeup Frame 0 CRC1 Register (0x32 – 0x33): WF0CRC1 ........................................................................................ 53

Wakeup Frame 0 Byte Mask 0 Register (0x34 – 0x35): WF0BM0 ................................................................................ 53

Wakeup Frame 0 Byte Mask 1 Register (0x36 – 0x37): WF0BM1 ................................................................................ 54

Wakeup Frame 0 Byte Mask 2 Register (0x38 – 0x39): WF0BM2 ................................................................................ 54

Wakeup Frame 0 Byte Mask 3 Register (0x3A – 0x3B): WF0BM3................................................................................ 54

0x3C – 0x3F: Reserved .................................................................................................................................................. 54

Wakeup Frame 1 CRC0 Register (0x40 – 0x41): WF1CRC0 ........................................................................................ 54

Wakeup Frame 1 CRC1 Register (0x42 – 0x43): WF1CRC1 ........................................................................................ 54

Wakeup Frame 1 Byte Mask 0 Register (0x44 – 0x45): WF1BM0 ................................................................................ 54

Wakeup Frame 1 Byte Mask 1 Register (0x46 – 0x47): WF1BM1 ................................................................................ 55

Wakeup Frame 1 Byte Mask 2 Register (0x48 – 0x49): WF1BM2 ................................................................................ 55

Wakeup Frame 1 Byte Mask 3 Register (0x4A – 0x4B): WF1BM3................................................................................ 55

0x4C – 0x4F: Reserved .................................................................................................................................................. 55

Wakeup Frame 2 CRC0 Register (0x50 – 0x51): WF2CRC0 ........................................................................................ 55

Wakeup Frame 2 CRC1 Register (0x52 – 0x53): WF2CRC1 ........................................................................................ 55

Wakeup Frame 2 Byte Mask 0 Register (0x54 – 0x55): WF2BM0 ................................................................................ 55

August 2009

M9999-083109-2.0

KSZ8851-32MQL Related Products

	KSZ8851-32MQL	KSZ8851-32MQLI
Description	Ethernet ICs 10/100BT Ethernet MAC + PHY with Generic (32-bit) Bus Interface (I-Temp)
Is it Rohs certified?	conform to	conform to
Maker	Microchip	Microchip
package instruction	QFP-128	FQFP,
Reach Compliance Code	compliant	compliant
Factory Lead Time	17 weeks	20 weeks
JESD-30 code	R-PQFP-G128	R-PQFP-G128
JESD-609 code	e3	e3
length	20 mm	20 mm
Humidity sensitivity level	3	3
Number of functions	1	1
Number of terminals	128	128
Maximum operating temperature	70 °C	85 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	FQFP	FQFP
Package shape	RECTANGULAR	RECTANGULAR
Package form	FLATPACK, FINE PITCH	FLATPACK, FINE PITCH
Peak Reflow Temperature (Celsius)	245	245
Certification status	Not Qualified	Not Qualified
Maximum seat height	3.4 mm	3.4 mm
Nominal supply voltage	1.8 V	1.8 V
surface mount	YES	YES
technology	CMOS	CMOS
Telecom integrated circuit types	ETHERNET TRANSCEIVER	ETHERNET TRANSCEIVER
Temperature level	COMMERCIAL	INDUSTRIAL
Terminal surface	MATTE TIN	MATTE TIN
Terminal form	GULL WING	GULL WING
Terminal pitch	0.5 mm	0.5 mm
Terminal location	QUAD	QUAD
Maximum time at peak reflow temperature	40	40
width	14 mm	14 mm
Base Number Matches	1	1

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