Features
•
•
•
•
•
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Very Low Power Design (≈ 50 mW)
Single IF Concept
2-bit ADC on Chip
Small QFN Package (28 Pins)
Highly Integrated, Few External Components
UHF6 Technology
Electrostatic sensitive device.
Observe precautions for handling.
GPS
Front-end IC
ATR0600
Description
With the growing importance of mobile communication, location awareness is a key
feature for more and more products and services. Due to its small size and minimal
power consumption, the GPS front-end IC ATR0600 is an ideal solution for mobile
applications and navigation systems.
Figure 1.
Block Diagram
96.76 MHz
1575.42 MHz
LC-BP
VS3
LNA
RFIN
Preliminary
Ant
BP NBP
BPI
NBPI
REF
VDIG
Dig. IF at 4.35 MHz
SIGH
SAW
RFNIN
VGA amp
BP-Filter
SIGL
SC 23.104 MHz
OR
AGCO
VCO
1478.6
MHz
64
1
1
4
Power
control
GC
PFD
XTO
P2
VS1
VS2
VS5
VS7
X
XTO
NXTO NX P1
23.104 MHz
Rev. 4536F–GPS–10/03
ATR0600 [Preliminary]
Functional
Description
The specification of GPS receivers for personal mobile applications strongly differs from
stand-alone GPS receiver specifications. One reason is the presence of strong blocking
signals from mobile transmitters which might cause unacceptable levels of degradation
in the carrier-to-noise ratio of a GPS system if not sufficiently suppressed. The other
reason is the requirements for very low power consumption.
The ATR0600 GPS receiver IC has been especially designed for GPS applications in
mobile phones. From this system point of view, it incorporates highest isolation between
GPS and cellular antennas, as well as low power consumption. The ATR0600 contains
a low-power single IF design and integrates a complete frequency synthesizer. It is fully
functional over a supply-voltage range of 2.7 V to 3.3 V and is housed in a 28-pin
QLN package.
The GPS receiver's input signal is a Direct Sequence Spread Spectrum (DSSS) signal
at 1575.42 MHz with a 1.023 Mbps Bi-Phase-Shift-Keying (BPSK) modulated spreading
code. As the input signal power at the antenna is approximately -140 dBm, the desired
signal is below the thermal noise floor.
LNA/Mixer Stage
The ATR0600 receives the L1 GPS signal via an external LNA. The LNA bandwidth
should be as narrow as possible to avoid interferences from out-of-band signals (espe-
cially from those of the 1800 GSM band).
Combined with the antenna the LNA provides a first filtering of the GPS signal. The LNA
in addition should have a power shutdown feature. The shutdown signal will be gener-
ated inside the digital section of the GPS receiver. The output of the LNA drives an
external SAW filter, which provides the image rejection for the mixer and the isolation of
the 1800-MHz GSM band. The output of the SAW filter drives a highly linear mixer which
down-converts the GPS signal to an IF of 97.76 MHz.
IF Stage
The mixer directly drives an external LC-bandpath filter. In order to provide the ultimate
selectivity of the GPS frequency before the A/D conversion of the receiver part, the
signal path of the ATR0600 combines an external filter and a second integrated filter.
We recommend to design the external filter as a 2-pole filter with quality factor Q > 25.
The output of the LC-filter drives an on-chip Variable Gain-Controlled amplifier (VGA)
which is combined with an integrated IF-bandpath filter to perform additional filtering of
GSM jamming signals. The AGC stage provides the additional gain needed to optimally
load the signal range of the following analog/digital converter. The AGC control loop can
be selected either on-chip close loop or open loop mode. Connecting the AGC_OUT
output directly to the AGC_CNTRL input activates the internal control loop.
In that case, the VGA control signal is passed to the VGA via an integrated buffer stage
including all necessary filtering (low-pass filter). The external control loop is closed by
the baseband IC ATR0620.
VGA Amplifier Stage
A/D Converter Stage
The output of the VGA drives the integrated 1.5-bit analog-to-digital converter stage,
which comprises two comparators and two output drivers in order to provide sign and
magnitude output bits to the baseband IC ATR0620. The comparator LOW- and HIGH-
thresholds (in Figure 1 on page 1 for SIGH and SIGL) are adjustable via external resis-
tor. The OR gate closes the internal AGC control loop.
The integrated power-control stage is controlled by the baseband IC ATR0620 via P1
and P2. The input signals control the shutdown of the reference crystal oscillator (P2) or
the shutdown of the whole RF section (P1).
Power Save Setting
Stage
3
4536F–GPS–10/03
.
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Supply voltage
Input voltage
Junction temperature
Storage temperature range
Symbol
V
S
V
in
T
j
T
stg
Value
3.7
3.7
125
-40 to +125
Unit
V
V
°C
°C
Thermal Resistance
Parameters
Junction ambient
Symbol
R
thJA
Value
125
Unit
K/W
Recommended Operating Conditions
Parameters
Supply voltage
Temperature range
Input frequency
Reference frequency
External IF filter (see Figure 13 on page 9)
Supply voltage digital interface, pin 27
V
DD
1.65 to 2.0
V
Symbol
V
S
Temp
f
in, mixer
f
ref
Value
2.7 to 3.3
-40 to +85
1575.42
23.104
Unit
V
°C
MHz
MHz
Electrical Characteristics
No.
1
1.1
Parameters
Common
Supply current
P1 = P2 = VPU
on
P1 = VPU
off
P2 = VPU
on
P1 = P2 = VPU
on
3, 6,
11,
19, 23
6
27
3, 6,
11,
19,
23, 27
1
I
S
I
XTO
I
DD
18
mA
A
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
1.2
1.3
Supply current XTO
Supply current digital
interface
Supply current (power
down)
2
250
mA
µA
A
A
1.4
P1 = P2 = VPU
OFF
I
S, pd
20
µA
A
1.5
1.6
Total gain
Noise figure
RFIN, RNIN matched,
to 50
W,
V
GC
= 2.2 V
G
N
F
95
6.9
dB
dB
B
C
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
4
ATR0600 [Preliminary]
4536F–GPS–10/03
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