PIC24FJXXXDA1/DA2/GB2/GA3/GC0
PIC24FJXXXDA1/DA2/GB2/GA3/GC0 Families Flash
Programming Specification
1.0
DEVICE OVERVIEW
Topics covered include:
1.0 Device Overview ....................................................... 1
2.0 Programming Overview of the
PIC24FJXXXDA1/DA2/GB2/GA3/GC0 Families.......... 2
3.0 Device Programming – ICSP ................................... 18
4.0 Device Programming – Enhanced ICSP .................. 33
5.0 The Programming Executive ................................... 51
6.0 Device Details ......................................................... 63
7.0 AC/DC Characteristics and Timing Requirements......... 66
This document defines the programming specification
for the PIC24FJXXXDA1/DA2/GB2/GA3/GC0 families
of 16-bit microcontrollers (MCUs). This programming
specification is required only for those developing pro-
gramming support for the PIC24FJXXXDA1/DA2/GB2/
GA3/GC0 families. Customers using only one of these
devices should use development tools that already
provide support for device programming.
This specification includes programming specifications
for the following devices:
• PIC24FJ128DA106
• PIC24FJ128DA110
• PIC24FJ128DA206
• PIC24FJ128DA210
• PIC24FJ128GB206
• PIC24FJ128GB210
• PIC24FJ64GA310
• PIC24FJ64GA308
• PIC24FJ64GA306
• PIC24FJ64GC010
• PIC24FJ64GC008
• PIC24FJ64GC006
• PIC24FJ256DA106
• PIC24FJ256DA110
• PIC24FJ256DA206
• PIC24FJ256DA210
• PIC24FJ256GB206
• PIC24FJ256GB210
• PIC24FJ128GA310
• PIC24FJ128GA308
• PIC24FJ128GA306
• PIC24FJ128GC010
• PIC24FJ128GC008
• PIC24FJ128GC006
2009-2012 Microchip Technology Inc.
DS39970E-page 1
PIC24FJXXXDA1/DA2/GB2/GA3/GC0
2.0
PROGRAMMING OVERVIEW
OF THE PIC24FJXXXDA1/DA2/
GB2/GA3/GC0 FAMILIES
The Enhanced In-Circuit Serial Programming
(Enhanced ICSP) protocol uses a faster method that
takes advantage of the Programming Executive (PE),
as illustrated in
Figure 2-1.
The Programming Execu-
tive provides all the necessary functionality to erase,
program and verify the chip through a small command
set. The command set allows the programmer to
program the PIC24FJXXXDA1/DA2/GB2/GA3/GC0
MCUs without having to deal with the low-level
programming protocols of the chip.
There are two methods of programming the
PIC24FJXXXDA1/DA2/GB2/GA3/GC0 families of
devices discussed in this programming specification.
They are:
• In-Circuit Serial Programming™ (ICSP™)
• Enhanced In-Circuit Serial Programming
(Enhanced ICSP)
The ICSP programming method is the most direct
method to program the device; however, it is also the
slower of the two methods. It provides native, low-level
programming capability to erase, program and verify
the chip.
Note:
The address of Special Function Register,
TBLPAG, has changed from 0x32 to 0x54
in PIC24FJXXXDA1/DA2/GB2/GA3/GC0
family devices.
In those cases where legacy programming
specification code from other device
families is used as a basis to implement
the PIC24FJXXXDA1/DA2/GB2/GA3/GC0
families’ programming specification, spe-
cial care must be taken to ensure all
references to TBLPAG, in any existing
code, are updated with the correct opcode
hex data for the mnemonic and operands
(as shown below).
FIGURE 2-1:
PROGRAMMING SYSTEM
OVERVIEW FOR
ENHANCED ICSP™
PIC24F Devices
Programmer
Programming
Executive
On-Chip Memory
PIC24FJXXXDA1/DA2/GB2/GA3/GC0 Families
Command
(Binary)
0000
Data
(Hex)
8802A0
MOV
Description
W0, TBLPAG
This specification is divided into major sections that
describe the programming methods independently.
Section 3.0 “Device Programming – ICSP”
describes
the In-Circuit Serial Programming method.
Section 4.0
“Device Programming – Enhanced ICSP”
describes
the Run-Time Self-Programming (RTSP) method.
All Other PIC24F Families
Command
(Binary)
0000
Data
(Hex)
880190
MOV
Description
W0, TBLPAG
DS39970E-page 2
2009-2012 Microchip Technology Inc.
PIC24FJXXXDA1/DA2/GB2/GA3/GC0
2.1
Power Requirements
FIGURE 2-2:
All PIC24FJXXXDA1/DA2/GB2/GA3/GC0 devices
power their core digital logic at a nominal 1.8V. To
simplify system design, all devices in the
PIC24FJXXXDA1/DA2/GB2/GA3/GC0 families incor-
porate an on-chip regulator that allows the device to
run its core logic from V
DD
. For the PIC24F128GA310
and PIC24FJ128GC010 families, the regulator is always
enabled, so there is no ENVREG pin on these devices.
The regulator provides power to the core from the other
V
DD
pins. A low-ESR capacitor (such as ceramic or tan-
talum) must be connected to the V
CAP
pin (see
Table 2-1
and
Figure 2-2).
This helps to maintain the stability of the
regulator. The specifications for core voltage and capac-
itance are listed in
Section 7.0 “AC/DC Characteristics
and Timing Requirements”.
CONNECTIONS FOR THE
ON-CHIP REGULATOR
Regulator Enabled (ENVREG tied to V
DD
):
3.3V
PIC24FJXXXDA1/DA2/GB2
V
DD
ENVREG
V
CAP
C
EFC
(10
F typ)
V
SS
2.2
Program Memory Write/Erase
Requirements
FIGURE 2-3:
CONNECTIONS FOR THE
V
BAT
PIN
The Flash program memory on PIC24FJXXXDA1/DA2/
GB2/GA3/GC0 devices has a specific write/erase
requirement that must be adhered to for proper device
operation. Any given word in memory must not be
written more than twice before erasing the page where
it is located. Thus, the easiest way to conform to this
rule is to write all of the data in a programming block,
within one write cycle. The programming methods
specified in this specification comply with this
requirement.
Note:
Writing to a location multiple times without
erasing is
not
recommended.
Regulator Enabled (V
BAT
tied to V
DD
or a Battery):
3.3V
PIC24FJXXXGA3/GC0
V
DD
V
BAT
V
CAP
C
EFC
(10
F typ)
V
SS
TABLE 2-1:
PIN DESCRIPTIONS (DURING PROGRAMMING)
During Programming
Pin Name
Pin Name
MCLR
ENVREG
(1)
V
DD
, AV
DD
and SV
DD
(2)
V
SS
, AV
SS
and SV
SS
(2)
V
CAP
PGECx
PGEDx
MCLR
ENVREG
V
DD
V
SS
V
CAP
PGECx
PGED
X
(1)
Pin Type
P
I
P
P
P
I
I/O
Programming Enable
Pin Description
Enable for On-Chip Voltage Regulator
Power Supply
Ground
On-Chip Voltage Regulator Output to the Core
Programming Pin Pairs 1, 2 and 3: Serial Clock
Programming Pin Pairs 1, 2 and 3: Serial Data
Legend:
I = Input, O = Output, P = Power
Note 1:
There is no ENVREG pin in the PIC24FJ128GA310 and PIC24FJ128GC010 families. The regulator is
always enabled and the ENVREG pin is replaced by the V
BAT
pin. It is recommended to connect the V
BAT
pin to the battery or V
DD
during programming.
2:
All power supply and ground pins must be connected, including analog supplies and ground (AV
DD
/AV
SS
and SV
DD
/SV
SS
, where implemented).
2009-2012 Microchip Technology Inc.
DS39970E-page 3
PIC24FJXXXDA1/DA2/GB2/GA3/GC0
2.3
Pin Diagrams
2.3.1
PGECx AND PGEDx PIN PAIRS
Figure 2-4
through
Figure 2-17
provide the pin dia-
grams for the PIC24FJXXXDA1/DA2/GB2/GA3/GC0
families. The pins that are required for programming
are listed in
Table 2-1
and are indicated in bold text in
the figures. Refer to the appropriate device data sheet
for complete pin descriptions.
All of the devices in the PIC24FJXXXDA1/DA2/GB2/
GA3/GC0 families have three separate pairs of pro-
gramming pins, labelled as PGEC1/PGED1, PGEC2/
PGED2 and PGEC3/PGED3. Any one of these pin pairs
may be used for device programming by either ICSP or
Enhanced ICSP. Unlike voltage supply and ground
pins, it is not necessary to connect all three pin pairs to
program the device. However, the programming
method must use both pins of the same pair.
FIGURE 2-4:
PIC24FJXXXDAX PIN DIAGRAM (64-PIN TQFP)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
RE4
RE3
RE2
RE1
RE0
RF1
RF0
ENVREG
V
CAP
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RE5
RE6
RE7
RG6
RG7
RG8
MCLR
RG9
V
SS
V
DD
PGEC3/AN5/C1INA/V
BUSON
/RP18/CN7/RB5
PGED3/AN4/C1INB/USBOEN/RP28/CN6/RB4
RB3
RB2
PGEC1/AN1/RP1/V
REF
-/CN3/RB1
PGED1/AN0/V
REF
+/RP0/CN2/RB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
RC14
RC13
RD0
RD11
RD10
RD9
RD8
V
SS
RC15
RC12
V
DD
RG2
RG3
V
USB
RF2
RF3
PIC24FJXXXDAX06
PGEC2/AN6/RP6/CN24/RB6
PGED2/AN7/RP7/RCV/CN25/RB7
AV
DD
AV
SS
RB8
RB9
RB10
RB11
V
SS
V
DD
DS39970E-page 4
RB12
RB13
RB14
RB15
RF4
RF5
2009-2012 Microchip Technology Inc.
PIC24FJXXXDA1/DA2/GB2/GA3/GC0
FIGURE 2-5:
PIC24FJXXXGA306 PIN DIAGRAM (64-PIN TQFP)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
RE4
RE3
RE2
RE1
RE0
RF1
RF0
V
BAT
V
CAP
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RE5
RE6
RE7
RG6
RG7
RG8
MCLR
RG9
V
SS
V
DD
PGEC3/AN5/C1INA/RP18/SEG2/CN7/RB5
PGED3/AN4/C1INB/RP28/SEG3/CN6/RB4
RB3
RB2
PGEC1/CV
REF
-/AN1/RP1/SEG6//CN3/RB1
PGED1/CV
REF
+/AN0/RP0/SEG7/PMA6/CN2/RB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
RC14
RC13
RD0
RD11
RD10
RD9
RD8
V
SS
RC15
RC12
V
DD
RG2
RG3
RF6
RF2
RF3
PIC24FJXXXGA306
PGEC2/AN6/RP6/LCDBIAS3/CN24/RB6
PGED2/AN7/RP7/CN25/RB7
AV
DD
AV
SS
RB8
RB9
RB10
RB11
V
SS
V
DD
2009-2012 Microchip Technology Inc.
RB12
RB13
RB14
RB15
RF4
RF5
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DS39970E-page 5
Embedded System
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