Freescale Semiconductor
Data Sheet: Advance Information
Document Number: MPC5674F
Rev. 10.1, 06/2015
MPC5674F
MPC5674F Microcontroller
Data Sheet
Covers: MPC5674F and MPC5673F
TEPBGA–416
27mm x 27mm
TEPBGA–516
27mm x 27mm
TEPBGA–324
23mm x 23mm
• Dual issue, 32-bit CPU core complex (e200z7)
– Compliant with the Power Architecture
®
embedded
category
– 16 KB I-Cache and 16 KB D-Cache
– Includes an instruction set enhancement allowing
variable length encoding (VLE), optional encoding of
mixed 16-bit and 32-bit instructions, for code size
footprint reduction
– Includes signal processing extension (SPE2) instruction
support for digital signal processing (DSP) and
single-precision floating point operations
• 4 MB on-chip flash
– Supports read during program and erase operations, and
multiple blocks allowing EEPROM emulation
• 256 KB on-chip general-purpose SRAM including 32 KB
of standby RAM
• Two direct memory access controller (eDMA2) blocks
– One supporting 64 channels
– One supporting 32 channels
• Interrupt controller (INTC)
• Frequency modulated phase-locked loop (FMPLL)
• Crossbar switch architecture for concurrent access to
peripherals, flash, or RAM from multiple bus masters
• External bus interface (EBI) for calibration and application
development (not available on all packages)
• System integration unit (SIU)
• Error correction status module (ECSM)
• Boot assist module (BAM) supports serial bootload via
CAN or SCI
• Two second-generation enhanced time processor units
(eTPU2) that share code and data RAM.
– 32 standard channels per eTPU2
– 24 KB code RAM
– 6 KB parameter (data) RAM
• Enhanced modular input output system supporting 32
unified channels (eMIOS) with each channel capable of
•
•
•
•
•
•
•
•
single action, double action, pulse width modulation
(PWM) and modulus counter operation
Four enhanced queued analog-to-digital converters
(eQADC)
– Support for 64 analog channels
– Includes one absolute reference ADC channel
– Includes eight decimation filters
Four deserial serial peripheral interface (DSPI) modules
Three enhanced serial communication interface (eSCI)
modules
Four controller area network (FlexCAN) modules
Dual-channel FlexRay controller
Nexus development interface (NDI) per IEEE-ISTO
5001-2003/5001-2008 standard
Device and board test support per Joint Test Action Group
(JTAG) (IEEE 1149.1)
On-chip voltage regulator controller regulates supply
voltage down to 1.2 V for core logic
© Freescale Semiconductor, Inc., 2008-2015. All rights reserved.
Table of Contents
1
2
3
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1 Orderable Parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.2 MPC567xF Family Differences . . . . . . . . . . . . . . . . . . . .4
MPC5674F Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3.1 324-ball TEPBGA Pin Assignments . . . . . . . . . . . . . . . .6
3.2 416-ball TEPBGA Pin Assignments . . . . . . . . . . . . . . . .9
3.3 516-ball TEPBGA Pin Assignments . . . . . . . . . . . . . . .14
3.4 Signal Properties and Muxing . . . . . . . . . . . . . . . . . . . .19
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .21
4.2.1 General Notes for Specifications at
Maximum Junction Temperature . . . . . . . . . . . .23
4.3 EMI (Electromagnetic Interference) Characteristics . . .24
4.4 ESD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.5 PMC/POR/LVI Electrical Specifications . . . . . . . . . . . .25
4.6 Power Up/Down Sequencing . . . . . . . . . . . . . . . . . . . .29
4.6.1 Power-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
4.6.2 Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . .30
4.6.3 Power Sequencing and POR Dependent on V
DDA
30
4.7 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .30
4.7.1 I/O Pad Current Specifications . . . . . . . . . . . . .33
4.7.2 I/O Pad V
DD33
Current Specifications . . . . . . . .34
4.7.3 LVDS Pad Specifications . . . . . . . . . . . . . . . . . 35
Oscillator and FMPLL Electrical Characteristics . . . . . 35
eQADC Electrical Characteristics . . . . . . . . . . . . . . . . 37
4.9.1 ADC Internal Resource Measurements . . . . . . 39
4.10 C90 Flash Memory Electrical Characteristics . . . . . . . 40
4.11 AC Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.11.1 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.11.2 Pad AC Specifications . . . . . . . . . . . . . . . . . . . 44
4.12 AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.12.1 Generic Timing Diagrams. . . . . . . . . . . . . . . . . 45
4.12.2 Reset and Configuration Pin Timing. . . . . . . . . 46
4.12.3 IEEE 1149.1 Interface Timing. . . . . . . . . . . . . . 47
4.12.4 Nexus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.12.5 External Bus Interface (EBI) Timing . . . . . . . . . 53
4.12.6 External Interrupt Timing (IRQ Pin) . . . . . . . . . 57
4.12.7 eTPU Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.12.8 eMIOS Timing . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.12.9 DSPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5.1 324-Pin Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5.2 416-Pin Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.3 516-Pin Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6 Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Appendix ASignal Properties and Muxing . . . . . . . . . . . . . . . . . . 73
Appendix BRevision History . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
4.8
4.9
4
MPC5674F Microcontroller Data Sheet, Rev. 10.1
2
Freescale Semiconductor
Ordering Information
1
1.1
Ordering Information
Orderable Parts
M PC 5674F F 3 M VR 3 R
Qualification status
Core code
Figure 1
and
Table 1
describe and list the orderable part numbers for the MPC5674F.
Note:
Not all options are
available on all
devices. Refer to
Table 1.
Device number
Fab Revision ID
Revision of Silicon
Temperature range
Package identifier
Operating frequency (MHz)
Tape and reel status
Temperature Range
M = –40 °C to 125 °C
Package Identifier
VZ = 324 BGA Pb-free
VR = 416 BGA Pb-free
VY = 516 BGA Pb-free
VV = 516 BGA SnPb
Operating Frequency
2 = 200 MHz
3 = 264 MHz
Tape and Reel Status
R = Tape and reel
(blank) = Trays
Qualification Status
P = Pre qualification
M = Fully spec. qualified, general market flow
S = Fully spec. qualified, automotive flow
Revision of Silicon
3 = Rev 3 (ATMC)
0 = Rev 0 (TSMC14)
Fab Revision ID
F = ATMC
K = TSMC14
Figure 1. MPC5674F Orderable Part Number Description
Table 1. Orderable Part Numbers
Speed (MHz)
1
Freescale Part Number
SPC5674FK0MVR3
SPC5674FK0MVY3
SPC5674FK0MVV3R
SPC5674FK0MVV3
SPC5674FK0MVY3R
SPC5674FK0MVY3
SPC5673FK0MVR2R
SPC5673FK0MVR2
SPC5673FK0MVV2R
SPC5673FK0MVV2
1
Operating Temperature
2
Min (T
L
)
–40 °C
–40 °C
–40 °C
–40 °C
–40 °C
–40 °C
–40 °C
–40 °C
–40 °C
–40 °C
Max (T
H
)
125 °C
125 °C
125 °C
125 °C
125 °C
125 °C
125 °C
125 °C
125 °C
125 °C
Package Description
Nominal
416 PBGA, no EBI, Pb-free
516 PBGA, w/EBI, Pb-free
516 PBGA, w/EBI, SnPb
516 PBGA, w/EBI, SnPb
516 PBGA, w/EBI, Pb-free
516 PBGA, w/EBI, Pb-free
416 PBGA, no EBI, Pb-free
416 PBGA, no EBI, Pb-free
324 PBGA, no EBI, Pb-free
324 PBGA, no EBI, Pb-free
264
264
264
264
264
264
200
200
200
200
Max
3
(f
MAX
)
270
270
270
200
270
270
200
200
200
200
For the operating mode frequency of various blocks on the device, see
Table 28.
MPC5674F Microcontroller Data Sheet, Rev. 10.1
Freescale Semiconductor
3
Ordering Information
2
3
The lowest ambient operating temperature is referenced by T
L
; the highest ambient operating temperature is referenced by T
H
.
Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency modulation (FM).
270 MHz parts allow for 264 MHz system clock + 2% FM.
1.2
MPC567xF Family Differences
Table 2. MPC567xF Family Differences
Feature
Package
Flash
SRAM
External bus
Serial
eSCI_A
eSCI_B
eSCI_C
SPI
DSPI_A
DSPI_B
DSPI_C
DSPI_D
eMIOS
eTPU2
eTPU_A
eTPU_B
ADC
eQADC_A
eQADC_B
1
Table 2
lists the differences between the MPC567xF devices. Refer to the
MPC5674F Reference Manual
for a full feature list
and comparison.
MPC5674F
416 BGA
516 BGA
4 MB
256 KB
Yes
(516 BGA only)
3
Yes
Yes
Yes
4
Yes
Yes
Yes
Yes
32 channel
64 channel
Yes (32 ch)
Yes (32 ch)
64 channel
Yes (64 ch)
1
MPC5674F
324 BGA
4 MB
256 KB
No
2
Yes
Yes
No
3
No
Yes
Yes
Yes
22 channel
47 channel
Yes (26 ch)
Yes (21 ch, no
TCRCLK)
48 channel
Yes (24 ch)
Yes (24 ch)
MPC5673F
416 BGA
516 BGA
3 MB
192 KB
Yes
(516 BGA only)
3
Yes
Yes
Yes
4
Yes
Yes
Yes
Yes
32 channel
64 channel
Yes
Yes
64 channel
Yes (64 ch)
1
MPC5673F
324 BGA
3 MB
192 KB
No
2
Yes
Yes
No
3
No
Yes
Yes
Yes
22 channel
47 channel
Yes (26 ch)
Yes (21 ch, no
TCRCLK)
48 channel
Yes (24 ch)
Yes (24 ch)
There are are two pairs of 24 channels plus 16 shared channels. This gives 64 channels total: 40 per
ADC (since 16 are shared).
MPC5674F Microcontroller Data Sheet, Rev. 10.1
4
Freescale Semiconductor
MPC5674F Blocks
2
2.1
MPC5674F Blocks
Block Diagram
MPC5674F
Interrupt
Controller
Figure 2
shows a top-level block diagram of the MPC5674F device.
Power™
e200z7 Core
SPE2
VLE
MMU
eDMA2
64 Channel
eDMA2
32 Channel
16K
I-Cache
16K
D-Cache
FlexRay
EBI
(Calibration
&
Development
Use)
Nexus
JTAG
Crossbar Switch
MPU
4MB
Flash
I/O
Bridge
SIU
256KB SRAM
(32K S/B)
Boot Assist
Module
I/O
Bridge
ECSM
DSPI
DSPI
DSPI
DSPI
eSCI
eSCI
eSCI
ADC
ADC
ADC
24KB
Code
RAM
AMux
LEGEND
ADC
ADCi
AMux
DECFIL
DSPI
EBI
ECSM
eDMA2
eMIOS
eQADC
– Analog to digital convertor
– ADC interface
– Analog multiplexer
– Decimation filter
– Deserial/serial peripheral interface
– External bus interface
– Error correction status module
– Enhanced direct memory access
– Enhanced modular I/O system
– Enhanced queued A/D converter module
eSCI
– Enhanced serial communications interface
eTPU2
– Enhanced time processing unit 2
FlexCAN–
Controller area network
MMU
– Memory management unit
MPU
– Memory protection unit
S/B
– Stand-by
SIU
– System integration unit
SPE2
– Signal processing engine 2
SRAM
– General-purpose static RAM
VLE
– Variable length instruction encoding
Figure 2. Block Diagram
3
Pin Assignments
The figures in this section show the primary pin function. For the full signal properties and muxing table, see
Appendix A,
Signal Properties and Muxing.
MPC5674F Microcontroller Data Sheet, Rev. 10.1
Freescale Semiconductor
5
ADC
eMIOS
32
Channel
eTPU2
32
Channel
6KB
Data
RAM
DECFILx8
FlexCAN
FlexCAN
FlexCAN
FlexCAN
eQADC eQADC
ADCi
ADCi
eTPU2
32
Channel
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