DATA SHEET
512MB DDR SDRAM SO-DIMM
EBD52UD6ADSA-E
(64M words
×
64 bits, 2 Ranks)
Description
The EBD52UD6ADSA is 64M words
×
64 bits, 2 ranks
Double Data Rate (DDR) SDRAM Small Outline Dual
In-line Memory Module, mounting 8 pieces of 512M
bits DDR SDRAM sealed in TSOP package. Read and
write operations are performed at the cross points of
the CK and the /CK. This high-speed data transfer is
realized by the 2 bits prefetch-pipelined architecture.
Data strobe (DQS) both for read and write are available
for high speed and reliable data bus design. By setting
extended mode register, the on-chip Delay Locked
Loop (DLL) can be set enable or disable. This module
provides high density mounting without utilizing surface
mount technology. Decoupling capacitors are mounted
beside each TSOP on the module board.
Features
•
200-pin socket type small outline dual in line memory
module (SO-DIMM)
PCB height: 31.75mm
Lead pitch: 0.6mm
Lead-free
•
2.5V power supply
•
Data rate: 333Mbps/266Mbps (max.)
•
2.5 V (SSTL_2 compatible) I/O
•
Double Data Rate architecture; two data transfers per
clock cycle
•
Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
•
Data inputs, outputs and DM are synchronized with
DQS
•
4 internal banks for concurrent operation
(Components)
•
DQS is edge aligned with data for READs; center
aligned with data for WRITEs
•
Differential clock inputs (CK and /CK)
•
DLL aligns DQ and DQS transitions with CK
transitions
•
Commands entered on each positive CK edge; data
referenced to both edges of DQS
•
Data mask (DM) for write data
•
Auto precharge option for each burst access
•
Programmable burst length: 2, 4, 8
•
Programmable /CAS latency (CL): 2, 2.5
•
Refresh cycles: (8192 refresh cycles /64ms)
7.8µs maximum average periodic refresh interval
•
2 variations of refresh
Auto refresh
Self refresh
Document No. E0604E10 (Ver. 1.0)
Date Published October 2004 (K) Japan
URL: http://www.elpida.com
Elpida
Memory , Inc. 2004
EBD52UD6ADSA-E
Pin Description
Pin name
A0 to A12
BA0, BA1
DQ0 to DQ63
/RAS
/CAS
/WE
/CS0, /CS1
CKE0, CKE1
CK0 to CK2
/CK0 to /CK2
DQS0 to DQS7
DM0 to DM7
SCL
SDA
SA0 to SA2
VDD
VDDSPD
VREF
VSS
VDDID
NC
Function
Address input
Row address
Column address
Data input/output
Row address strobe command
Column address strobe command
Write enable
Chip select
Clock enable
Clock input
Differential clock input
Input and output data strobe
Input mask
Clock input for serial PD
Data input/output for serial PD
Serial address input
Power for internal circuit
Power for serial EEPROM
Input reference voltage
Ground
VDD identification flag
No connection
A0 to A12
A0 to A9
Bank select address
Data Sheet E0604E10 (Ver. 1.0)
4
EBD52UD6ADSA-E
Serial PD Matrix
Byte No. Function described
0
1
2
3
4
5
6
7
8
9
Number of bytes utilized by module
manufacturer
Total number of bytes in serial PD
device
Memory type
Number of row address
Number of column address
Number of DIMM ranks
Module data width
Module data width continuation
DDR SDRAM cycle time, CL = X
-6B
-7A, -7B
10
SDRAM access from clock (tAC)
-6B
-7A, -7B
11
12
13
14
15
16
17
18
19
20
21
22
23
DIMM configuration type
Refresh rate/type
Primary SDRAM width
Error checking SDRAM width
SDRAM device attributes:
Minimum clock delay back-to-back
column access
SDRAM device attributes:
Burst length supported
SDRAM device attributes: Number of
banks on SDRAM device
SDRAM device attributes: /CS latency
SDRAM device attributes: /WE latency
SDRAM module attributes
SDRAM device attributes: General
Minimum clock cycle time at
CL = X –0.5
-6B, -7A
-7B
24
Maximum data access time (tAC) from
clock at CL = X –0.5
-6B
-7A, -7B
25 to 26
27
Minimum row precharge time (tRP)
-6B
-7A, -7B
28
Bit7
1
0
0
0
0
0
0
0
Bit6
0
0
0
0
0
0
1
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
0
1
1
0
0
Bit5
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
0
0
0
1
1
Bit4
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
1
1
1
Bit3
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
1
0
0
1
Bit2
0
0
1
1
0
0
0
0
1
0
1
0
1
0
0
0
0
0
1
1
1
0
0
0
0
1
0
0
1
0
0
0
0
1
Bit1
0
0
1
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
Bit0
0
0
1
1
0
0
0
0
0
0
1
0
1
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
0
0
0
Hex value
80H
08H
07H
0DH
0AH
02H
40H
00H
04H
60H
75H
70H
75H
00H
82H
10H
00H
01H
0EH
04H
0CH
01H
02H
20H
C0H
75H
A0H
70H
75H
00H
48H
50H
30H
3CH
18ns
20ns
12ns
15ns
0.7ns
*1
Comments
128 bytes
256 bytes
DDR SDRAM
13
10
2
64 bits
0
SSTL2
CL = 2.5*
1
Voltage interface level of this assembly 0
0
0
0
0
0
1
0
0
0
0
0
0.7ns
*1
0.75ns
None
*1
7.8µs
Self refresh
×
16
Not used
1 CLK
2,4,8
4
2, 2.5
0
1
Unbuffered
VDD ± 0.2V
CL = 2*
1
SDRAM device attributes: /CAS latency 0
0
0
0
1
0
1
0
0
0
0
0
0.75ns*
1
Minimum row active to row active delay
(tRRD)
0
-6B
-7A, -7B
0
Data Sheet E0604E10 (Ver. 1.0)
5
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