EBD52UD6ADSA-E datasheet, PDF - EEWORLD Datasheet

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EBD52UD6ADSA-E: Description512MB DDR SDRAM SO-DIMM (64M words x 64 bits, 2 Ranks); File Size186KB，19 Pages; ManufacturerELPIDA; Websitehttp://www.elpida.com/en

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EBD52UD6ADSA-E Overview

512MB DDR SDRAM SO-DIMM (64M words x 64 bits, 2 Ranks)

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DATA SHEET

512MB DDR SDRAM SO-DIMM

EBD52UD6ADSA-E

(64M words

64 bits, 2 Ranks)

Description

The EBD52UD6ADSA is 64M words

64 bits, 2 ranks

Double Data Rate (DDR) SDRAM Small Outline Dual

In-line Memory Module, mounting 8 pieces of 512M

bits DDR SDRAM sealed in TSOP package. Read and

write operations are performed at the cross points of

the CK and the /CK. This high-speed data transfer is

realized by the 2 bits prefetch-pipelined architecture.

Data strobe (DQS) both for read and write are available

for high speed and reliable data bus design. By setting

extended mode register, the on-chip Delay Locked

Loop (DLL) can be set enable or disable. This module

provides high density mounting without utilizing surface

mount technology. Decoupling capacitors are mounted

beside each TSOP on the module board.

Features

•

200-pin socket type small outline dual in line memory

module (SO-DIMM)



PCB height: 31.75mm



Lead pitch: 0.6mm



Lead-free

•

2.5V power supply

•

Data rate: 333Mbps/266Mbps (max.)

•

2.5 V (SSTL_2 compatible) I/O

•

Double Data Rate architecture; two data transfers per

clock cycle

•

Bi-directional, data strobe (DQS) is transmitted

/received with data, to be used in capturing data at

the receiver

•

Data inputs, outputs and DM are synchronized with

DQS

•

4 internal banks for concurrent operation

(Components)

•

DQS is edge aligned with data for READs; center

aligned with data for WRITEs

•

Differential clock inputs (CK and /CK)

•

DLL aligns DQ and DQS transitions with CK

transitions

•

Commands entered on each positive CK edge; data

referenced to both edges of DQS

•

Data mask (DM) for write data

•

Auto precharge option for each burst access

•

Programmable burst length: 2, 4, 8

•

Programmable /CAS latency (CL): 2, 2.5

•

Refresh cycles: (8192 refresh cycles /64ms)



7.8µs maximum average periodic refresh interval

•

2 variations of refresh



Auto refresh



Self refresh

Document No. E0604E10 (Ver. 1.0)

Date Published October 2004 (K) Japan

URL: http://www.elpida.com

Elpida

Memory , Inc. 2004

EBD52UD6ADSA-E Related Products

	EBD52UD6ADSA-E	EBD52UD6ADSA-6B-E	EBD52UD6ADSA-7A-E	EBD52UD6ADSA-7B-E
Description	512MB DDR SDRAM SO-DIMM (64M words x 64 bits, 2 Ranks)	512MB DDR SDRAM SO-DIMM (64M words x 64 bits, 2 Ranks)	512MB DDR SDRAM SO-DIMM (64M words x 64 bits, 2 Ranks)	512MB DDR SDRAM SO-DIMM (64M words x 64 bits, 2 Ranks)
Is it Rohs certified?	-	conform to	conform to	conform to
Maker	-	ELPIDA	ELPIDA	ELPIDA
Parts packaging code	-	SODIMM	SODIMM	SODIMM
package instruction	-	DIMM, DIMM200,24	DIMM, DIMM200,24	DIMM, DIMM200,24
Contacts	-	200	200	200
Reach Compliance Code	-	unknow	unknow	unknow
ECCN code	-	EAR99	EAR99	EAR99
access mode	-	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST
Maximum access time	-	0.7 ns	0.75 ns	0.75 ns
Other features	-	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	-	167 MHz	133 MHz	133 MHz
I/O type	-	COMMON	COMMON	COMMON
JESD-30 code	-	R-XZMA-N200	R-XZMA-N200	R-XZMA-N200
memory density	-	4294967296 bi	4294967296 bi	4294967296 bi
Memory IC Type	-	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE
memory width	-	64	64	64
Number of functions	-	1	1	1
Number of ports	-	1	1	1
Number of terminals	-	200	200	200
word count	-	67108864 words	67108864 words	67108864 words
character code	-	64000000	64000000	64000000
Operating mode	-	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	-	70 °C	70 °C	70 °C
organize	-	64MX64	64MX64	64MX64
Output characteristics	-	3-STATE	3-STATE	3-STATE
Package body material	-	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
encapsulated code	-	DIMM	DIMM	DIMM
Encapsulate equivalent code	-	DIMM200,24	DIMM200,24	DIMM200,24
Package shape	-	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	-	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	-	260	260	260
power supply	-	2.5 V	2.5 V	2.5 V
Certification status	-	Not Qualified	Not Qualified	Not Qualified
refresh cycle	-	8192	8192	8192
self refresh	-	YES	YES	YES
Maximum slew rate	-	2.38 mA	2.02 mA	2.02 mA
Maximum supply voltage (Vsup)	-	2.7 V	2.7 V	2.7 V
Minimum supply voltage (Vsup)	-	2.3 V	2.3 V	2.3 V
Nominal supply voltage (Vsup)	-	2.5 V	2.5 V	2.5 V
surface mount	-	NO	NO	NO
technology	-	CMOS	CMOS	CMOS
Temperature level	-	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	-	NO LEAD	NO LEAD	NO LEAD
Terminal pitch	-	0.6 mm	0.6 mm	0.6 mm
Terminal location	-	ZIG-ZAG	ZIG-ZAG	ZIG-ZAG
Maximum time at peak reflow temperature	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED

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