NJW1109
Headphone Amplifier with Electronic Volume
s
GENERAL DESCRIPTION
The
NJW1109
is a headphone amplifier with electronic volume. It
includes widely gain adjustable volume, +20 to –80 dB, and mute
2
function. These are controlled by I C bus. The
NJW1109
is
suitable for headphone output on TV set.
s
PACKAGE OUTLINE
NJW1109D
NJW1109M
NJW1109V
s
FEATURES
q
Operating Voltage
q
Electronic Volume
2
q
I C Bus Interface
q
Bi-CMOS Technology
q
Package Outline
s
BLOCK DIAGRAM
7.5 to 10 V
+20dB to -80dB / 0.5dB step, Mute
DIP14, DMP14, SSOP14
CAPa
SDA SCL
IC
Interface
2
ADR
OUTa
IN a
VOL
IN b
VOL
OUTb
Bias
Vref
CAPb
s
PIN FUNCTION
No.
1
1
14
2
3
4
5
7
8
6
7
SYMBOL
V+ GND
V+
OUTb
N.C.
CAPb
INb
ADR
SDA
FUNCTION
Power Supply
Bch Output
No Connect
Balance control click noise
absorbing capacitor connect
terminal
Bch Input
I
2
C Bus Slave Address
Select
I
2
C Bus Data Input
No.
8
9
10
11
12
13
14
SYMBOL
SCL
Vref
INa
CAPa
N.C.
OUTa
GND
FUNCTION
I
2
C Bus Clock Input
Reference voltage stabilized
capacitor connect terminal
Ach Input
Volume control click noise
absorbing capacitor connect
terminal
No Connect
Ach Output
Ground
–1–
NJW1109
s
ABSOLUTE MAXIMUM RATING (Ta=25°C)
°
PARAMETER
SYMBOL
Supply Voltage
Power Dissipation
Operating Temperature Range
Storage Temperature Range
V
+
RATING
12
500 (DIP14)
500* (DMP14)
440* (SSOP14)
-20 to +75
-40 to +125
UNIT
V
mW
°C
°C
P
D
Topr
Tstg
*(Note) EIA/JEDEC STANDARD Test board(76.2 x 114.3 x 1.6mm, 2layers, FR-4)mounting
s
ELECTRICAL CHARACTERISTICS
(V =9V, V
IN
=-20dBV, f=1kHz, R
L
=100Ω,
VOL = 0dB
, Ta=25
°C
)
q
POWER SUPPLY
+
PARAMETER
Operating Voltage
Operating Current
Reference Voltage
q
AMPLIFIER
SYMBOL
V
+
TEST CONDITION
No Signal
MIN.
7.5
-
4.0
TYP.
9
5
4.5
MAX.
10
8
5.0
UNIT
V
mA
V
I
CC
V
REF
SYMBOL
G
VMAX
G
VMIN
∆Gv
V
IM
P
O
THD
CS
Mute
V
NO1
V
NO2
PSRR
SYMBOL
V
ADRH
V
ADRL
PARAMETER
Volume Maximum Gain
Volume Minimum Gain
Voltage Gain Channel Balance
Maximum Input Voltage
Output Power
Total Harmonic Distortion
Channel Separation
Mute Level
Output Noise Voltage 1
Output Noise Voltage 2
Power Supply Ripple Rejection
q
CONTROL
TEST CONDITION
VOL = +20dB setting
VOL = -80dB setting
VOL = 0dB setting
VOL = -10dB setting
MIN.
18
-1.5
8.9
(2.8)
70
-
70
-
-
-
-
MIN.
V /2
-
+
TYP.
20
-80
0
9.5
(3.0)
100
0.1
80
-100
-95
(18)
-105
(5.6)
70
TYP.
-
-
MAX.
22
1.5
-
-
1
-
-90
-85
(56)
-95
(18)
-
MAX.
-
1.0
UNIT
dB
dB
dBV
(Vrms)
mW
%
dB
dB
dBV
(µVrms)
THD=3%
VOL = 10dB,
THD=10%
VOL = 0dB setting
Rg=600Ω, Vin = 0dBV
VOL =
Mute, Vin = 0dBV
Rg=0Ω, A-Weighted
VOL =
Mute
dBV
(µVrms)
Rg=0Ω, A-Weighted
Vripple=-20dBV, Rg=0Ω
dB
UNIT
V
V
PARAMETER
High Level Input Voltage
Low Level Input Voltage
TEST CONDITION
High : Slave Address 84H
Low : Slave Address 80H
–2–
NJW1109
s
I C BUS CHARACTERISTICS
2
2
(SDA, SCL)
SYMBOL
V
IL
V
IH
V
hys
V
OL
t
of
t
SP
I
i
C
i
f
SCL
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
r
t
f
t
SU:STO
t
BUF
C
b
V
nL
V
nH
MIN.
0.0
2.5
0.25
0
20+0.1C
b
I C BUS Load Conditions: Pull up resistance 4kΩ (Connected to +5V), Load capacitance 200pF (Connected to GND)
PARAMETER
Low Level Input Voltage
High Level Input Voltage
Hysteresis of Schmitt trigger inputs
LOW level output voltage (3mA at SDA pin)
Output fall time from V
IHmin
to V
ILmax
with
a bus capacitance from 10pF to 400pF
Pulse width of spikes which must be suppressed by the input filter
TYP.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MAX.
1.5
5.0
-
0.4
250
50
10
10
400
-
-
-
-
0.9
-
300
300
-
-
400
-
-
UNIT
V
V
V
V
ns
ns
µA
pF
kHz
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
pF
V
V
0
-10
-
-
0.6
1.3
0.6
0.6
0
100
-
-
0.6
1.3
-
0.5
1
Input current each I/O pin with an input voltage between 0.1V
DD
and 0.9V
DDmax
Capacitance for each I/O pin
SCL clock frequency
Hold time (repeated) START condition.
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
Data hold time
Data set-up time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
Bus free time between a STOP and START condition
Capacitive load for each bus line
Noise margin at the LOW level
Noise margin at the HIGH level
C
b
; total capacitance of one bus line in pF.
SDA
t
f
t
r
t
SU:DAT
t
f
t
HD:STA
t
SP
t
r
t
BUF
SCL
t
HD:STA
S
t
LOW
t
HD:DAT
t
HIGH
t
SU:STA
Sr
t
SU:STO
P
S
–3–
NJW1109
s
TERMINAL DESCRIPTION
No.
SYMBOL
FUNCTION
EQUIVALENT CIRCUIT
VOLTAGE
17k
5
10
INb
INa
Bch Input
V+/2
Ach Input
2
13
OUTb
OUTa
Bch Output
V+/2
Ach Output
12k
4
CAPb
Balance control click noise
absorbing capacitor connect
terminal
8k
3.8V
11
CAPa
Volume control click noise
absorbing capacitor connect
terminal
8k
3.1V
–4–
NJW1109
s
TERMINAL DESCRIPTION
No.
SYMBOL
FUNCTION
EQUIVALENT CIRCUIT
VOLTAGE
4k
6
ADR
I C Bus Slave Address
Select
12k
2
-
7
8
SDA
SCL
I C Bus Data Input
I C Bus Clock Input
12k
2
2
4k
-
200k
1.3k
9
Vref
Reference voltage stabilized
capacitor connect terminal
200k
V+/2
1
V+
Power Supply
-
-
14
GND
Ground
-
-
–5–
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