IS61NLP12832-5TQ datasheet, PDF

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IS61NLP12832-5TQ: DescriptionPIPELINE NO WAIT STATE BUS SRAM; File Size159KB，20 Pages; ManufacturerISSI(Integrated Silicon Solution Inc.); Websitehttp://www.issi.com/

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IS61NLP12832-5TQ Overview

PIPELINE NO WAIT STATE BUS SRAM

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IS61NP12832 IS61NP12836 IS61NP25618

IS61NLP12832 IS61NLP12836 IS61NLP25618

128K x 32, 128K x 36 and 256K x 18

PIPELINE 'NO WAIT' STATE BUS SRAM

ISSI

PRELIMINARY INFORMATION

OCTOBER 2000

FEATURES

•

100 percent bus utilization

No wait cycles between Read and Write

Internal self-timed write cycle

Individual Byte Write Control

Single R/W (Read/Write) control pin

Clock controlled, registered address,

data and control

Interleaved or linear burst sequence control

using MODE input

Three chip enables for simple depth expansion

and address pipelining for TQFP

Power Down mode

Common data inputs and data outputs

CKE

pin to enable clock and suspend operation

JEDEC 100-pin TQFP, 119 PBGA package

Single +3.3V power supply (± 5%)

NP Version: 3.3V I/O Supply Voltage

NLP Version: 2.5V I/O Supply Voltage

Industrial temperature available

DESCRIPTION

The 4 Meg 'NP' product family feature high-speed,

low-power synchronous static RAMs designed to provide

a burstable, high-performance, 'no wait' state, device for

network and communications customers. They are

organized as 131,072 words by 32 bits, 131,072 words

by 36 bits and 262,144 words by 18 bits, fabricated with

ISSI

's advanced CMOS technology.

Incorporating a 'no wait' state feature, wait cycles are

eliminated when the bus switches from read to write, or

write to read. This device integrates a 2-bit burst counter,

high-speed SRAM core, and high-drive capability outputs

into a single monolithic circuit.

All synchronous inputs pass through registers are controlled

by a positive-edge-triggered single clock input. Operations

may be suspended and all synchronous inputs ignored

when Clock Enable,

CKE

is HIGH. In this state the internal

device will hold their previous values.

All Read, Write and Deselect cycles are initiated by the

ADV input. When the ADV is HIGH the internal burst

counter is incremented. New external addresses can be

loaded when ADV is LOW.

Write cycles are internally self-timed and are initiated by

the rising edge of the clock inputs and when

is LOW.

Separate byte enables allow individual bytes to be written.

A burst mode pin (MODE) defines the order of the burst

sequence. When tied HIGH, the interleaved burst sequence

is selected. When tied LOW, the linear burst sequence is

selected.

FAST ACCESS TIME

Symbol

Parameter

Clock Access Time

Cycle Time

Frequency

-150*

3.8

6.7

150

-133

4.2

7.5

133

-100

100

Units

MHz

*This speed available only in NP version

This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the

Integrated Silicon Solution, Inc. — 1-800-379-4774

PRELIMINARY INFORMATION

11/30/00

Rev. 00C

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