K4R271669D
Overview
The Rambus Direct RDRAM™ is a general purpose high-
performance memory device suitable for use in a broad
range of applications including communications, graphics,
video, and any other application where high bandwidth and
low latency are required.
The 128Mbit Direct Rambus DRAMs (RDRAM®) are
extremely high-speed CMOS DRAMs organized as 8M
words by 16. The use of Rambus Signaling Level (RSL)
technology permits to 800MHz transfer rates while using
conventional system and board design technologies. Direct
RDRAM devices are capable of sustained data transfers at
1.25 ns per two bytes (10ns per sixteen bytes).
The architecture of the Direct RDRAMs allows the highest
sustained bandwidth for multiple, simultaneous randomly
addressed memory transactions. The separate control and
data buses with independent row and column control yield
over 95% bus efficiency. The Direct RDRAM's 32 banks
support up to four simultaneous transactions.
System oriented features for mobile, graphics and communi-
cations include power management, byte masking.
Preliminary
Direct RDRAM
™
SAMSUNG 001
K4R271669D-TCxx
Figure 1: Direct RDRAM CSP Package
The 128Mbit Direct RDRAMs are offered in a horizontal
center-bond fanout CSP.
Key Timing Parameters/Part Numbers
Speed
Organiza-
tion
256Kx16x32s
a
Bin
I/O
Freq.
MHz
t
RAC
(Row
Access
Time) ns
Features
♦
Highest sustained bandwidth per DRAM device
-
1.6GB/s
sustained data transfer rate
- Separate control and data buses for maximized
efficiency
- Separate row and column control buses for
easy scheduling and highest performance
- 32 banks: four transactions can take place simul-
taneously at full bandwidth data rates
♦
Low latency features
Part Number
-CS8
800
45
K4R271669D-T
b
CS8
a.
“32s”
- 32 banks which use a
“split”
bank architecture.
b.
“T”
- Lead free consumer package.
- Write buffer to reduce read latency
- 3 precharge mechanisms for controller flexibility
- Interleaved transactions
♦
Advanced power management:
- Multiple low power states allows flexibility in power
consumption versus time to transition to active state
- Power-down self-refresh
♦
Organization: 1Kbyte pages and 32 banks, x 16
- x16 organization for low cost applications
♦
Uses Rambus Signaling Level (RSL) for up to 800MHz
operation
♦
WBGA package(54 Balls)
Page 1
Version 1.0 Dec. 2001
K4R271669D
Preliminary
Direct RDRAM
™
Table 2: Pin Description
Signal
SIO1,SIO0
I/O
I/O
Type
CMOS
a
CMOS
a
# Pins
center
2
Description
Serial input/output. Pins for reading from and writing to the control regis-
ters using a serial access protocol. Also used for power management.
Command input. Pins used in conjunction with SIO0 and SIO1 for reading
from and writing to the control registers. Also used for power manage-
ment.
Serial clock input. Clock source used for reading from and writing to the
control registers
Supply voltage for the RDRAM core and interface logic.
Supply voltage for the RDRAM analog circuitry.
Supply voltage for CMOS input/output pins.
Ground reference for RDRAM core and interface.
Ground reference for RDRAM analog circuitry.
Data byte A. Eight pins which carry a byte of read or write data between
the Channel and the RDRAM.
Clock from master. Interface clock used for receiving RSL signals from
the Channel. Positive polarity.
Clock from master. Interface clock used for receiving RSL signals from
the Channel. Negative polarity
Logic threshold reference voltage for RSL signals
Clock to master. Interface clock used for transmitting RSL signals to the
Channel. Negative polarity.
Clock to master. Interface clock used for transmitting RSL signals to the
Channel. Positive polarity.
Row access control. Three pins containing control and address informa-
tion for row accesses.
Column access control. Five pins containing control and address informa-
tion for column accesses.
Data byte B.Eight pins which carry a byte of read or write data between
the Channel and the RDRAM.
No Connection.
CMD
I
1
SCK
I
CMOS
a
1
V
DD
V
DDa
V
CMOS
GND
GNDa
DQA7..DQA0
I/O
RSL
b
RSL
b
RSL
b
6
1
2
9
1
8
CFM
I
1
CFMN
I
1
V
REF
CTMN
I
RSL
b
RSL
b
RSL
b
RSL
b
RSL
b
1
1
CTM
I
1
RQ7..RQ5 or
ROW2..ROW0
RQ4..RQ0 or
COL4..COL0
DQB7..
DQB0
NC
I
3
I
5
I/O
8
2
54
Total pin count per package
a. All CMOS signals are high-true; a high voltage is a logic one and a low voltage is logic zero.
b. All RSL signals are low-true; a low voltage is a logic one and a high voltage is logic zero.
Page 3
Version 1.0 Dec. 2001
Electronics Design Contest
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