K4S56323LF - F(H)E/N/S/C/L/R
2M x 32Bit x 4 Banks Mobile SDRAM in 90FBGA
FEATURES
• VDD/VDDQ = 2.5V/2.5V
• LVCMOS compatible with multiplexed address.
• Four banks operation.
• MRS cycle with address key programs.
-. CAS latency (1, 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
• EMRS cycle with address key programs.
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation.
• Special Function Support.
-. PASR (Partial Array Self Refresh).
-. Internal TCSR (Temperature Compensated Self Refresh)
• DQM for masking.
• Auto refresh.
•
•
•
•
64ms refresh period (4K cycle).
Commercial Temperature Operation (-25°C ~ 70°C).
Extended Temperature Operation (-25°C ~ 85°C).
90Balls FBGA ( -FXXX -Pb, -HXXX -Pb Free).
Mobile-SDRAM
GENERAL DESCRIPTION
The K4S56323LF is 268,435,456 bits synchronous high data
rate Dynamic RAM organized as 4 x 2,097,152 words by 32 bits,
fabricated with SAMSUNG’s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock and I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst lengths and programmable latencies allow the same
device to be useful for a variety of high bandwidth and high per-
formance memory system applications.
ORDERING INFORMATION
Part No.
K4S56323LF-F(H)E/N/S/C/L/R60
K4S56323LF-F(H)E/N/S/C/L/R75
K4S56323LF-F(H)E/N/S/C/L/R1H
K4S56323LF-F(H)E/N/S/C/L/R1L
Max Freq.
166MHz(CL=3)
133MHz(CL=3),111MHz(CL=2)
111MHz(CL=2)
111MHz(CL=3)*1
LVCMOS
90 FBGA Pb
(Pb Free)
Interface
Package
- F(H)E/N/S : Normal/Low/Super Low Power, Extended Temperature(-25°C ~ 85°C)
- F(H)C/L/R : Normal/Low/Super Low Power, Commercial Temperature(-25°C ~ 70°C)
NOTES :
1. In case of 40MHz Frequency, CL1 can be supported.
2. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake.
Please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for any specific pur
pose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use.
1
May 2004
K4S56323LF - F(H)E/N/S/C/L/R
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to V
ss
Voltage on V
DD
supply relative to V
ss
Storage temperature
Power dissipation
Short circuit current
Symbol
V
IN
, V
OUT
V
DD
, V
DDQ
T
STG
P
D
I
OS
Value
-1.0 ~ 3.6
-1.0 ~ 3.6
Mobile-SDRAM
Unit
V
V
°C
W
mA
-55 ~ +150
1.0
50
NOTES:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= -25 to 85°C for Extended, -25 to 70°C for Commercial)
Parameter
Supply voltage
V
DDQ
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
V
IH
V
IL
V
OH
V
OL
I
LI
2.3
0.8 x V
DDQ
-0.3
V
DDQ
-0.2
-
-10
2.5
-
0
-
-
-
2.7
V
DDQ
+ 0.3
0.3
-
0.2
10
V
V
V
V
V
uA
1
2
I
OH
= -0.1mA
I
OL
= 0.1mA
3
Symbol
V
DD
Min
2.3
Typ
2.5
Max
2.7
Unit
V
Note
NOTES :
1. VIH (max) = 3.0V AC.The overshoot voltage duration is
≤
3ns.
2. VIL (min) = -1.0V AC. The undershoot voltage duration is
≤
3ns.
3. Any input 0V
≤
VIN
≤
VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs.
4. Dout is disabled, 0V
≤
VOUT
≤
VDDQ.
CAPACITANCE
(V
DD
= 2.5V, T
A
= 23°C, f = 1MHz, V
REF
=0.9V
±
50 mV)
Pin
Clock
RAS, CAS, WE, CS, CKE
DQM
Address
DQ
0
~ DQ
31
Symbol
C
CLK
C
IN
C
IN
C
ADD
C
OUT
Min
-
-
-
-
-
Max
4.0
4.0
4.0
4.0
6.0
Unit
pF
pF
pF
pF
pF
Note
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May 2004
K4S56323LF - F(H)E/N/S/C/L/R
DC CHARACTERISTICS
Mobile-SDRAM
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= -25 to 85°C for Extended, -25 to 70°C for Commercial)
Version
Parameter
Symbol
Test Condition
-60
Operating Current
(One Bank Active)
Precharge Standby Current
in power-down mode
Burst length = 1
t
RC
≥
t
RC
(min)
I
O
= 0 mA
CKE
≤
V
IL
(max), t
CC
= 10ns
110
-75
100
-1H
-1L
Unit
Note
I
CC1
100
90
mA
1
I
CC
2P
0.5
mA
0.5
20
mA
8
4
mA
2
30
mA
I
CC
2PS CKE & CLK
≤
V
IL
(max), t
CC
=
∞
I
CC
2N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during
20ns
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
CKE
≤
V
IL
(max), t
CC
= 10ns
Precharge Standby Current
in non power-down mode
I
CC
2NS
Active Standby Current
in power-down mode
I
CC
3P
I
CC
3PS CKE & CLK
≤
V
IL
(max), t
CC
=
∞
I
CC
3N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during
20ns
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
I
O
= 0 mA
Page burst
4Banks Activated
t
CCD
= 2CLKs
t
RC
≥
t
RC
(min)
-E/C
-N/L
Active Standby Current
in non power-down mode
(One Bank Active)
I
CC
3NS
20
mA
Operating Current
(Burst Mode)
I
CC
4
120
100
90
90
mA
1
Refresh Current
I
CC
5
200
180
170
150
mA
uA
2
4
5
1500
600
Max 40
450
400
350
Max 85/70
600
450
400
uA
°C
Self Refresh Current
I
CC
6
CKE
≤
0.2V
-S/R
Internal TCSR
Full Array
1/2 of Full Array
1/4 of Full Array
3
6
NOTES:
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Internal TCSR can be supported.
In commercial Temp : Max 40°C/Max 70°C, In extended Temp : Max 40°C/Max 85°C
4. K4S56323LF-F(H)E/C**
5. K4S56323LF-F(H)N/L**
6. K4S56323LF-F(H)S/R**
7. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ).
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May 2004
FPGA/CPLD
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