CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T
J
= T
C
= T
A
Electrical Specifications
PARAMETER
SUPPLY
I
S
I
SD
ANALOG
V
OL
V
OH
I
SC
PSRR
t
D
V
AC
V
MIS
V
DROOP
R
INH
REG
BG
DIGITAL
V
IH
V
IL
F
CLK
t
S
t
H
t
LC
t
CE
t
DCO
R
SDIN
T
PULSE
Duty Cycle
F_OSC
INL
DNL
Supply Current
V
S
= 15V, V
SD
= 5V, V
REFH
= 13V, V
REFL
= 2V,
R
L
= 1.5k and
C
L
= 200pF to 0V, T
A
= +25°C, unless
otherwise specified.
CONDITIONS
MIN
TYP
MAX
UNIT
DESCRIPTION
No load
15
0.17
18
0.35
mA
mA
Digital Supply Current
Output Swing Low
Output Swing High
Short Circuit Current
Power Supply Rejection Ratio
Program to Out Delay
Accuracy Referred to the Ideal Value
Channel to Channel Mismatch
Droop Voltage
Input Resistance @ V
REFH
, V
REFL
Load Regulation
Band Gap
Sinking 5mA (V
REFH
= 15V, V
REFL
= 0)
Sourcing 5mA (V
REFH
= 15V, V
REFL
= 0)
R
L
= 10
V
S
+ is moved from 14V to 16V
Code = 512
Code = 512
14.85
100
45
50
14.95
140
60
4
20
2
1
34
150
mV
V
mA
dB
ms
mV
mV
2
mV/ms
k
I
OUT
= 5mA step
1.1
0.5
1.3
1.5
1.6
mV/mA
V
Logic 1 Input Voltage
Logic 0 Input Voltage
Clock Frequency
Setup Time
Hold Time
Load to Clock Time
Clock to Load Line
Clock to Out Delay Time
S
DIN
Input Resistance
Minimum Pulse Width for EXT_OSC
Signal
Duty Cycle for EXT_OSC Signal
Internal Refresh Oscillator Frequency
Integral Nonlinearity Error
Differential Nonlinearity Error
OSC_Select = 0
Negative edge of SCLK
2
1
5
20
20
20
20
10
1
5
50
21
1.3
0.5
V
V
MHz
ns
ns
ns
ns
ns
G
µs
%
kHz
LSB
LSB
FN7393 Rev 2.00
September 21, 2010
Page 2 of 10
EL5525
Pin Descriptions
PIN NUMBER
1
2
3
4
5
6, 11, 16
7
8, 9, 17
10
12
13
14, 24, 28, 35
15
18
19
20
21
22
23
25
26
27
29
30
31
32
33
34
36
37
38
PIN NAME
ENA
SDI
SCLK
SDO
EXT_OSC
VS
VSD
NC
OSC_SELECT
REFH
REFL
GND
CAP
OUTR
OUTQ
OUTP
OUTO
OUTN
OUTM
OUTL
OUTK
OUTJ
OUTI
OUTH
OUTG
OUTF
OUTE
OUTD
OUTC
OUTB
OUTA
Analog Input
Analog Input
Power
Analog
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
PIN TYPE
Logic Input
Logic Input
Logic Input
Logic Output
Input/Output
Power
Power
PIN DESCRIPTION
Chip select, low enables data input to logic
Serial data input
Serial data clock
Serial data output
Oscillator pin for synchronizing
Positive supply voltage for analog circuits (4.5V to 16.5V)
Positive power supply for digital circuites (3.3V to 5V)
Not connected
Oscillator select, “0” = internal, “1” = external
High reference voltage
Low reference voltage
Ground
Decoupling capacitor for internal reference
Channel R output voltage
Channel Q output voltage
Channel P output voltage
Channel O output voltage
Channel N output voltage
Channel M output voltage
Channel L output voltage
Channel K output voltage
Channel J output voltage
Channel I output voltage
Channel H output voltage
Channel G output voltage
Channel F output voltage
Channel E output voltage
Channel D output voltage
Channel C output voltage
Channel B output voltage
Channel A output voltage
FN7393 Rev 2.00
September 21, 2010
Page 3 of 10
EL5525
Typical Performance Curves
DIFFERENTIAL NONLINEARITY (LSB)
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
10
V
S
= 15V
V
SD
= 5V
210
V
REFH
= 13V
V
REFL
= 2V
410
610
810
1010
INL (LSB)
0.5
REFH = 13V, REFL = 2V
1.5
1
0
-0.5
-1
0
200
400
600
CODE
800
1000
1200
INPUT CODE
FIGURE 1. DIFFERENTIAL NONLINEARITY vs CODE
FIGURE 2. INTEGRAL NONLINEARITY ERROR
V
S
= V
REFH
= 15V
V
S
= V
REFH
= 15V
0mA
5mA
C
L
= 4.7nF
R
S
= 20
5V
5mA/DIV
5mA
0mA
C
L
=1nF
R
S
= 20
5mA/DIV
200mV/DIV
C
L
= 1nF
R
S
= 20
C
L
= 180pF
M = 400ns/DIV
C
L
= 180pF
M = 400ns/DIV
C
L
= 4.7nF
R
S
= 20
200mV/DIV
FIGURE 3. TRANSIENT LOAD REGULATION (SOURCING)
FIGURE 4. TRANSIENT LOAD REGULATION (SINKING)
SCLK
SCLK
SDA
ENA
OUTA
SDA
ENA
OUTA
M = 200µs/DIV
M = 200µs/DIV
FIGURE 5. LARGE SIGNAL RESPONSE (RISING FROM 0V
TO 8V)
FIGURE 6. SMALL SIGNAL RESPONSE (FALLING FROM
200mV TO 100mV)
FN7393 Rev 2.00
September 21, 2010
Page 4 of 10
EL5525
General Description
The EL5525 provides a versatile method of providing the
reference voltages that are used in setting the transfer
characteristics of LCD display panels. The V/T
(Voltage/Transmission) curve of the LCD panel requires that
a correction is applied to make it linear; however, if the panel
is to be used in more than one application, the final curve
may differ for different applications. By using the EL5525,
the V/T curve can be changed to optimize its characteristics
according to the required application of the display product.
Each of the eight reference voltage outputs can be set with a
10-bit resolution. These outputs can be driven to within
50mV of the power rails of the EL5525. As all of the output
buffers are identical, it is also possible to use the EL5525 for
applications other than LCDs where multiple voltage
references are required that can be set to 10 bit accuracy.
together, connect the SDO pin to the SDI pin on the next
chip. While the ENA is held low, the 16m-bit data is loaded to
the SDI input of the first chip. The first 16-bit data will go to
the last chip and the last 16-bit data will go to the first chip.
While the ENA is held high, all addressed outputs will be
updated simultaneously.
The Serial Timing Diagram and parameters table show the
timing requirements for three-wire signals.
The serial data has a minimum length of 16 bits, the MSB
(most significant bit) is the first bit in the signal. The bits are
allocated to the following functions (also refer to Table 1).
• Bit 15 is always set to a zero
• Bits 14 through 10 select the channel to be written to, these
are binary coded with channel A = 0, and channel R = 17
• The 10-bit data is on bits 9 through 0. Some examples of
data words are shown in Table 3.
TABLE 1. CONTROL BITS LOGIC TABLE
BIT
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
NAME
Test
A4
A3
A2
A1
A0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DESCRIPTION
Always 0
Channel Address
Channel Address
Channel Address
Channel Address
Channel Address
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Digital Interface
The EL5525 uses a simple 3-wire SPI compliant digital
interface to program the outputs. The EL5525 can support
the clock rate up to 5MHz.
Serial Interface
The EL5525 is programmed through a three-wire serial
interface. The start and stop conditions are defined by the
ENA signal. While the ENA is low, the data on the SDI (serial
data input) pin is shifted into the 16-bit shift register on the
positive edge of the SCLK (serial clock) signal. The MSB
(bit 15) is loaded first and the LSB (bit 0) is loaded last (see
Table 1). After the full 16-bit data has been loaded, the ENA
is pulled high and the addressed output channel is updated.
The SCLK is disabled internally when the ENA is high. The
SCLK must be low before the ENA is pulled low.
To facilitate the system designs that use multiple EL5525
chips, a buffered serial output of the shift register (SDO pin)
is available. Data appears on the SDO pin at the 16th falling
SCLK edge after being applied to the SDI pin.
To control the multiple EL5525 chips from a single three-wire
serial port, just connect the ENA pins and the SCLK pins
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