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ELANSC300-25VC

Description
Highly Integrated, Low-Power, 32-Bit Microcontroller
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size865KB,139 Pages
ManufacturerAMD
Websitehttp://www.amd.com
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ELANSC300-25VC Overview

Highly Integrated, Low-Power, 32-Bit Microcontroller

ELANSC300-25VC Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerAMD
Parts packaging codeQFP
package instructionLFQFP, QFP208,1.2SQ,20
Contacts208
Reach Compliance Codeunknow
Has ADCNO
Address bus width24
bit size32
maximum clock frequency14.336 MHz
DAC channelNO
DMA channelYES
External data bus width16
JESD-30 codeS-PQFP-G208
JESD-609 codee0
length28 mm
Number of I/O lines
Number of terminals208
Maximum operating temperature70 °C
Minimum operating temperature
PWM channelNO
Package body materialPLASTIC/EPOXY
encapsulated codeLFQFP
Encapsulate equivalent codeQFP208,1.2SQ,20
Package shapeSQUARE
Package formFLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply3.3/5 V
Certification statusNot Qualified
Maximum seat height1.6 mm
speed25 MHz
Maximum supply voltage3.6 V
Minimum supply voltage3 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width28 mm
uPs/uCs/peripheral integrated circuit typeMICROCONTROLLER
PRELIMINARY
Élan
SC300
Highly Integrated, Low-Power, 32-Bit Microcontroller
DISTINCTIVE CHARACTERISTICS
n
Highly integrated, single-chip CPU and system
logic
– Optimized for embedded PC applications
– Combines 32 bit, x86 compatible, low-voltage
CPU with memory controller, PC/AT peripheral
controllers, real-time clock, and PLL clock gener-
ators
– 0.7 micron, low-voltage, CMOS process, fully
static
n
Enhanced Am386
®
SXLV CPU core
– 25 MHz or 33 MHz operating frequencies
– 3.3 V core, 3.3 V or 5 V memory and I/O
– Low-power, fully static design for long battery life
– System Management Mode (SMM) for power
management control
n
Integrated power management functions
– Internal clock generators (using multiple Phase-
Locked Loops and one external 32-KHz crystal)
– Supports CPU System Management Mode
(SMM)
– Multiple operating modes: High Speed PLL, Low
Speed PLL, Doze, Sleep, Suspend, and Off. Fully
static design allows stopped clock.
– Comprehensive control of system and peripheral
clocks
– Five external power management control pins
– Suspend refresh of DRAM array
– Clock switching during ISA cycles
– Low power consumption: 0.12 mW typical
Suspend mode power
– Simultaneous multiple-voltage I/O pads operate
at either 3.3 V or 5 V. Core operates at 3.3 V for
minimum power consumption.
n
Integrated memory controller
– Controls symmetrically addressable DRAM or
asymmetrical 512 Kbyte x 8 bit or 1 Mbyte x 16 bit
DRAM or SRAM as main memory
– Zero wait-state access with 70 ns, Page mode
DRAMs
– Supports up to 16 Mbyte system memory
– Supports up to 16 Mbyte of application ROM/
Flash, and 320 Kbyte direct ROM BIOS access.
Also supports shadow RAM
– Fully PC/AT compatible
n
Integrated PC/AT-compatible peripheral logic
– One programmable interval timer (fully 8254
compatible)
– Two programmable interrupt controllers (8259A
compatible)
– Two DMA controllers (8237A compatible)
– Built-in real-time clock (146818A compatible),
with an additional 114 bytes of RAM
– Internal Phase-Locked Loops (PLL) generate all
clocks from single 32.768 kHz crystal input
n
Bus configurations
– 16-bit data path
– Optional bus configurations:
— Internal LCD controller with subset ISA
— 386 Local Bus mode with subset ISA
— Maximum ISA Bus mode
– Four programmable chip selects
– Built-in 8042 chip select
n
Serial port controller (16450 UART compatible)
n
Bidirectional parallel port with EPP
n
Integrates two PCMCIA Version 2.1 slots
n
Integrated CGA-compatible LCD controller
– Fully 6845 compatible
– 16 gray levels in Text mode; 2 or 4 levels in
Graphics mode
– Supports the following LCD Panel Sizes:
— 320 x 240 single scan (2 bpp)
— 640 x 200 single/dual scan (1 bpp)
— 480 x 320 single scan (1 bpp)
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this product
without notice.
Publication#
18514
Rev:
D
Amendment/0
Issue Date:
October 1997

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Is it Rohs certified? incompatible incompatible incompatible - - - incompatible incompatible
Maker AMD AMD AMD - - - AMD AMD
Parts packaging code QFP QFP QFP - - - QFP QFP
package instruction LFQFP, QFP208,1.2SQ,20 FQFP, QFP208,1.2SQ,20 LFQFP, QFP208,1.2SQ,20 - - - FQFP, QFP208,1.2SQ,20 FQFP, QFP208,1.2SQ,20
Contacts 208 208 208 - - - 208 208
Reach Compliance Code unknow unknow unknow - - - unknow unknow
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