®
EMIF04-10006F2
IPAD™
4 LINES EMI FILTER
AND ESD PROTECTION
MAIN PRODUCT CHARACTERISTICS
Where EMI filtering in ESD sensitive equipment is
required:
■
Mobile phones and communication systems
■
Computers, printers and MCU Boards
DESCRIPTION
The EMIF04-10006F2 is a highly integrated
devices designed to suppress EMI/RFI noise in all
systems
subjected
to
electromagnetic
interferences. The EMIF04 flip-chip packaging
means the package size is equal to the die size.
This filter includes an ESD protection circuitry
which prevents the device from destruction when
subjected to ESD surges up 15kV. This device
includes four EMIF filters and 4 separated ESD
diodes.
BENEFITS
■
EMI symmetrical (I/O) low-pass filter
■
High efficiency in EMI filtering
■
Lead free package
■
Very low PCB space consuming:
2.92mm x 1.29mm
■
Very thin package: 0.65 mm
■
High efficiency in ESD suppression
(IEC61000-4-2 level 4)
■
High reliability offered by monolithic integration
■
High reducing of parasitic elements through
integration and wafer level packaging.
COMPLIES WITH THE FOLLOWING STANDARDS:
IEC 61000-4-2 level 4:
15kV (air discharge)
8kV (contact discharge)
MIL STD 883E - Method 3015-6 Class 3: 30kV
®
Flip-Chip
(15 Bumps)
Table 1: Order Code
Part Number
EMIF04-10006F2
Marking
FS
Figure 1: Pin Configuration (ball side)
9
8
7
6
5
4
3
2
1
D3
Gnd
D4
I4
I3
Gnd
O3
I2
I1
Gnd
D1
A
B
O4
O2
O1
D2
C
TM:
IPAD is a trademark of STMicroelectronics.
September 2004
REV. 1
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EMIF04-10006F2
Figure 2: Basic Cell Configuration
100Ω
100Ω
Input 1
30pF
30pF
Output 1
Input 4
30pF
30pF
Output 4
100Ω
Input 2
30pF
30pF
Output 2
D1
30pF
30pF
D2
100Ω
Input 3
30pF
30pF
Output 3
D3
30pF
30pF
D4
Table 2: Absolute Ratings
(limiting values)
Symbol
Parameter and test conditions
P
R
DC power per resistance
P
T
T
j
T
op
T
stg
Total DC power per package
Maximum junction temperature
Operating temperature range
Storage temperature range
Value
0.1
0.6
125
- 40 to + 85
125
Unit
W
W
°C
°C
°C
Table 3: Electrical Characteristics
(T
amb
= 25 °C)
Symbol
Parameter
V
BR
Breakdown voltage
I
RM
V
RM
V
CL
R
d
I
PP
R
I/O
C
line
Symbol
V
BR
I
RM
R
I/O
C
line
Leakage current @ V
RM
Stand-off voltage
Clamping voltage
Dynamic impedance
Peak pulse current
Series resistance between Input
and output
Capacitance per line
Test conditions
I
R
= 1 mA
V
RM
= 3.3 V per line
I = 10 mA
V
R
= 2.5 V, F = 1 MHz, 30 mV (on filter cells)
80
50
Min.
5.5
I
I
F
V
F
V
CL
V
BR
V
RM
I
RM
I
R
V
I
PP
Typ.
7
100
60
Max.
9
500
120
70
Unit
V
nA
Ω
pF
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EMIF04-10006F2
Figure 3: S21 (dB) attenuation measurements
and Aplac simulation
0.00
dB
-12.50
Figure 4: Analog crosstalk measurements
Aplac 7.62 User: ST Microelectronics
00
dB
-25
i3_o2.s2p
-25.00
-50
-37.50
-75
Measurement
Simulation
f/Hz
-50.00
100.0k
-100
1.0M
10.0M
100.0M
1.0G
f/Hz
100k
1M
10M
100M
1G
Figure 5: Digital crosstalk measurements
Figure 6: ESD response to IEC61000-4-2 (+15kV
air discharge) on one imput V(in) and one output
V(out)
Figure 7: ESD response to IEC61000-4-2 (–15kV
air discharge) on one imput V(in) and one output
V(out)
Figure 8: Line capacitance versus applied
voltage for filter
C(pF)
100
90
80
70
60
50
40
30
20
10
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
F=1MHz
V
osc
=30mV
RMS
T
j
=25°C
V
R
(V)
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EMIF04-10006F2
Figure 9: Aplac model
Rbump
Ii*
Lbump
Rs=100
Lbump
Rbump
Oi*
sub
Cz=41pF@0V
Cbump
Rsub
Cz=41pF@0V
Rsub
Cbump
Rsub
Rbump
Oi * = Output of each filter cell
Ii* = Input of each filter cell
sub
Lbump
Rbump
Dj *
Lbump
Lbump
Rbump
Di*
Cgnd
Lgnd
Cz=41pF@0V
Cbump
Rsub
With Dj* = D1 & D3
And Di* = D2 & D4
Cz=41pF@0V
Rsub
Cbump
Rgnd
sub
EMIF04-10006F2 model
Ground return for each GND bump
Figure 10: Aplac parameters
aplacvar RS
aplacvar Cz
aplacvar Lbump
aplacvar Rbump
aplacvar Cbump
aplacvar Rsub
aplacvar Rgnd
aplacvar Lgnd
aplacvar Cgnd
100
Ω
41 pF
50 pH
20 m
1.2 pF
100 m
100 m
100 pH
0.15 pF
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EMIF04-10006F2
Figure 11: Order code
EMIF
EMI Filter
Number of lines
Information
x = resistance value (Ohms)
z = capacitance value / 10(pF)
or
3 letters = application
2 digits = version
Package
F = Flip-Chip
x = 1: 500µm, Bump = 315µm
= 2: Leadfree Pitch = 500µm, Bump = 315µm
yy
-
xxx zz
Fx
Figure 12: FLIP-CHIP Package Mechanical Data
315µm ± 50
500µm ± 50
250µm ± 50
435µm ± 50
650µm ± 65
50
1µ
m
±5
2.92mm ± 50µm
Figure 13: Foot print recommendations
Figure 14: Marking
400
1.29mm ± 50µm
0
Copper pad Diameter :
250µm recommended , 300µm max
Dot, ST logo
xx = marking
z = packaging
location
yww = datecode
(y = year
ww = week)
545
545
E
Solder stencil opening : 330µm
Solder mask opening recommendation :
340µm min for 300µm copper pad diameter
x x z
y w w
100
230
All dimensions in µm
5/7
FPGA/CPLD
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