* Impedance is 2 ohms for ±2KV differential and common mode to comply with NEBS GR-1089 limits. Maximum load capacitance is required for these tests.
#
Tests above ±2KV will be performed for information purposes to IEC/EN66100-4-5 with 12ohm impedance, differential & common mode.
STATUS INDICATORS
LED NAME
Input
Input
Input
LED MODE
OK
OV/UV WARNING
OFF OR FAULT
LED STATE/OPERATION
Solid Green
Blinking Green
Off
DESCRIPTION
Input voltage operating within normal specified range
Input voltage operating in:
1) overvoltage warning, or
2) undervoltage warning range
Input voltage operating:
1) above overvoltage range, or
2) below undervoltage range, or
3) not present
Main output and standby output enabled with no power supply
warning or fault detected
Standby output enabled with no power supply warning or fault
detected
Power supply warning detected as per PMBus STATUS_X reporting
bytes
•
Power supply fault detected as per PMBus STATUS_X reporting
Output
Output
Output
Output
POWER GOOD
STANDBY
WARNING
FAULT
Solid Green
Blinking Green
Blinking Amber
Solid Amber
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D1U54P-W-650-12-HBxC.A02
Page 3 of 9
54mm 1U Front End AC-DC Power Supply Converter
bytes
•
•
D1U54P-W-650-12-HBxC Series
LED fault/warning operation follows PMBus fault/warning reporting status flags but will not be 'sticky';(i.e. if the fault stimulus is removed, even though the actual fault/warning is still showing (still “sticky” and not cleared),
the relevant LED will revert to normal (non -fault) operation.
STATUS AND CONTROL SIGNALS
Signal Name
INPUT_OK (AC Source)
I/O
Output
Description
The signal output is driven high when input source is available and within acceptable limits. The
output is driven low to indicate loss of input power.
There is a minimum of 1ms pre-warning time before the signal is driven low prior to the PWR_OK
signal going low. The power supply must ensure that this interface signal provides accurate status
when AC power is lost.
The signal is asserted, driven high, by the power supply to indicate that all outputs are valid. If any of
the outputs fail then this output will be hi-Z or driven low. The output is driven low to indicate that the
Main output is outside of lower limit of regulation (11.4Vdc).
Interface Details
Pulled up internally via 10K to 3.3Vdc.
A logic high >2.0Vdc
A logic low <0.8Vdc
Driven low by internal CMOS buffer
(open drain output).
Pulled up internally via 10K to 3.3Vdc.
A logic high >2.0Vdc
A logic low <0.8Vdc
Driven low by internal CMOS buffer
(open drain output).
Pulled up internally via 10K to 3.3Vdc.
A logic high >2.0Vdc
A logic low <0.8Vdc
Driven low by internal CMOS buffer
(open drain output).
Passive connection to +VSB_Return.
A logic low <0.8Vdc
Pulled up internally via 10K to 3.3Vdc.
A logic high >2.0Vdc
A logic low <0.8Vdc
Input is via CMOS Schmitt trigger
buffer.
Pulled up internally via 10K to 3.3Vdc.
A logic high >2.0Vdc
A logic low <0.8Vdc
Input is via CMOS Schmitt trigger
b ffvoltage between the limits of 0 and
DC
+3.3Vdc.
PW_OK (Output OK)
Output
SMB_ALERT
(FAULT/WARNING)
Output
The signal output is driven low to indicate that the power supply has detected a warning or fault and is
intended to alert the system. This output must be driven high when the power is operating correctly
(within specified limits).
The signal will revert to a high level when the warning/fault stimulus (that caused the alert) is
removed.
The signal is used to detect the presence (installed) of a PSU by the host system. The signal is
connected to PSU logic SGND within the power module.
This signal is pulled up internally to the internal housekeeping supply (within the power supply). The
power supply main 12Vdc output will be enabled when this signal is pulled low to +VSB_Return.
In the low state the signal input shall not source more than 1mA of current. The 12Vdc output will be
disabled when the input is driven higher than 2.4V, or open circuited. Cycling this signal shall clear
latched fault conditions.
This signal is used during hot swap to disable the main output during hot swap extraction. The input is
pulled up internally to the internal housekeeping supply (within the power supply).
The signal is provided on a short (lagging pin) and should be connected to +VSB_Return.
An analogue input that is used to set the address of the internal slave devices (EEPROM and
microprocessor) used for digital communications.
Connection of a suitable resistor to +VSB_Return, in conjunction with an internal resistor divider
chain, will configure the required address.
A serial clock line compatible with PMBus
TM
Power Systems Management Protocol Part 1 – General
Requirements Rev 1.1.
No additional internal capacitance is added that would affect the speed of the bus.
The signal is provided with a series isolator device to disconnect the internal power supply bus in the
event that the power module is unpowered,
A serial data line compatible with PMBus
TM
Power Systems Management Protocol Part 1 – General
Requirements Rev 1.1.
The signal is provided with a series isolator device to disconnect the internal power supply bus in the
event that the power module is unpowered,
Remote sense connections intended to be connected at and sense the voltage at the point of load.
The voltage sense will interact with the internal module regulation loop to compensate for voltage
drops due to connection resistance between the output connector and the load.
If remote sense compensation is not required then the voltage can be configured for local sense by:
1.
V1_SENSE directly connected to power blades 6 to 10 (inclusive)
2.
V1_SENSE_RTN directly connected to power blades 1 to 5 (inclusive)
The current sharing signal is connected between sharing units (forming an ISHARE bus). It is an
input and/or an output (bi-directional analogue bus) as the voltage on the line controls the current
share between sharing units. A power supply will respond to a change in this voltage but a power
supply can also change the voltage depending on the load drawn from it. On a single unit the
voltage on the pin (and the common ISHARE bus would read 8VDC at 100% load (module
capability). For two identical units sharing the same 100% load this would read 4VDC for perfect
current sharing (i.e. 50% module load capability per unit).
PRESENT_L
(Power Supply Absent)
PS_ON
(Power Supply
Enable/Disable
PS_KILL
Output
Input
Input
ADDR (Address Select)
Input
SCL (Serial Clock)
Both
V
IL
is 0.8V maximum
V
OL
is 0.4V maximum when sinking
3mA
V
IH
is 2.1V minimum
V
IL
is 0.8V maximum
V
OL
is 0.4V maximum when sinking
3mA
V
IH
is 2.1V minimum
Compensation for a up to 0.12Vdc
total connection drop (output and
return connections).
SDA (Serial Data)
Both
V1_SENSE
V1SENSE_RTN
Input
ISHARE
Bi-
Directional
Analogue
Bus
Analogue voltage:
+8V maximum; 10K to +12V_RTN
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D1U54P-W-650-12-HBxC.A02
Page 4 of 9
54mm 1U Front End AC-DC Power Supply Converter
TIMING SPECIFICATIONS
Turn-On Delay & Output Rise Time:
Power On Delay; Rise Time and Signaling
AC Input
AC Input
V1 PS_ON Delay
D1U54P-W-650-12-HBxC Series
VSB
VSB Rise
Time
VSB
VSB Power On Delay
V1; 12V
V1 Rise
Time
V1; 12V
V1 PS_ON Delay
V1 Power On Delay
PS_ON
PS_ON
AC_OK
AC_OK
Delay
PW_OK
Delay
AC_OK
PW_OK
PW_OK
1. The turn-on delay after application of AC input within the operating range shall as defined in the following tables.
2. The output rise times shall be measured from 10% of the nominal output to the lower limit of the regulation band as defined in the following tables.
Time
Vsb Rise time
V1 Rise time
Vsb Power-on-delay
V1 Power-on-delay
V1 PS_ON delay
V1 PWOK delay
ACOK detect
TIMING SPECIFICATIONS
Turn-Off (Shutdown by PS_ON)
Min
100ms
20ms
100ms
100ms
300ms
Max
200ms
120ms
2700ms
3000ms
150ms
300ms
2000ms
Turn Off Fall Time and Signaling
AC Input
VSB
Turn-Off Timing
V1 Fall time
V1 PS_OFF delay
PW_OK delay off
Min
-
0ms
1.0ms
Max
-
5ms
Notes
Must be monotonic
V1; 12V
V1 PS_OFF Delay
V1 Falltime
PS_ON
AC_OK
PWOK delayoff
PW_OK
1. Note this characteristic is applicable for the main 12Vdc output shutdown from PS_ON pulled high.
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