ADVANCED INFORMATION
MX26L3220
32M-BIT [2M x 16] CMOS
MULTIPLE-TIME-PROGRAMMABLE EPROM
FEATURES
•
2,097,152 x 16 byte structure
•
Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program
operations
•
Status Reply
- Data polling & Toggle bits provide detection of
program and erase operation completion
•
12V ACC input pin provides accelerated program
capability
•
Low Vcc write inhibit is equal to or less than 2.5V
•
Compatible with JEDEC standard
•
High Performance
- Fast access time: 90/120ns (typ.)
- Fast program time: 70s/chip (typ.)
- Fast erase time: 90s/chip (typ.)
•
Output voltages and input voltages on the device is
deterined by the voltage on the VI/O pin.
- VI/O voltage range:1.65V~3.6V
•
10 years data retention
•
Package
- 44-Pin SOP
- 48-Pin TSOP
- 48-Ball CSP
•
Low Power Consumption
- Low active read current: 17mA (typ.) at 5MHz
- Low standby current: 30uA (typ.)
•
Minimum 100 erase/program cycle
GENERAL DESCRIPTION
The MX26L3220 is a 32M bit MTP EPROM
TM
organized
as 2M bytes of 16 bits. MXIC's MTP EPROM
TM
offer the
most cost-effective and reliable read/write non-volatile
random access memory. The MX26L3220 is packaged in
44-pin SOP, 48-pin TSOP and 48-ball CSP. It is designed
to be reprogrammed and erased in system or in standard
EPROM programmers.
The standard MX26L3220 offers access time as fast as
90ns, allowing operation of high-speed microprocessors
without wait states. To eliminate bus contention, the
MX26L3220 has separate chip enable (CE) and output
enable OE controls. MXIC's MTP EPROM
TM
augment
EPROM functionality with in-circuit electrical erasure and
programming. The MX26L3220 uses a command register
to manage this functionality.
MXIC's MTP EPROM
TM
technology reliably stores
memory contents even after 100 erase and program
cycles. The MXIC cell is designed to optimize the erase
and program mechanisms. In addition, the combination of
advanced tunnel oxide processing and low internal
electric fields for erase and programming operations
produces reliable cycling.
The MX26L3220 uses a 2.7V to 3.6V VCC supply to
perform the High Reliability Erase and auto Program/
Erase algorithms.
The highest degree of latch-up protection is achieved with
MXIC's proprietary non-epiprocess. Latch-up protection
is proved for stresses up to 100 milliamps on address and
data pin from -1V to VCC +1V.
P/N:PM0826
REV. 0.5, JAN. 29, 2002
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MX26L3220
AUTOMATIC PROGRAMMING
The MX26L3220 is word programmable using the Auto-
matic Programming algorithm. The Automatic Program-
ming algorithm makes the external system do not need
to have time out sequence nor to verify the data pro-
grammed. The typical chip programming time at room
temperature of the MX26L3220 is less than 90 seconds.
All data are latched on the rising edge of WE or CE,
whichever happens later.
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm require the user
to only write program set-up commands (including 2 un-
lock write cycle and A0H) and a program command (pro-
gram data and address). The device automatically times
the programming pulse width, provides the program veri-
fication, and counts the number of sequences. A status
bit similar to DATA polling and a status bit toggling be-
tween consecutive read cycles, provide feedback to the
user as to the status of the programming operation.
MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality, relia-
bility, and cost effectiveness. The MX26L3220 electri-
cally erases all bits simultaneously using Fowler-Nord-
heim tunneling. The bytes are programmed by using the
EPROM programming mechanism of hot electron injec-
tion.
During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. After the state machine
has completed its task, it will allow the command regis-
ter to respond to its full command set.
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 50 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
Typical erasure at room temperature is accomplished in
less than 45 seconds. The Automatic Erase algorithm
automatically programs the entire array prior to electrical
erase. The timing and verification of electrical erase are
controlled internally within the device.
AUTOMATIC ERASE ALGORITHM
MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stand-
ard microprocessor write timings. The device will auto-
matically pre-program and verify the entire array. Then
the device automatically times the erase pulse width,
provides the erase verification, and counts the number
of sequences. A status bit toggling between consecu-
tive read cycles provides feedback to the user as to the
status of the programming operation.
Register contents serve as inputs to an internal state-
machine which controls the erase and programming cir-
cuitry. During write cycles, the command register inter-
nally latches address and data needed for the program-
ming and erase operations. All address are latched on
the falling edge of WE or CE, whichever happens later.
P/N:PM0826
REV. 0.5, JAN. 29, 2002
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