MX23L4100
4M-BIT MASK ROM (8/16 BIT OUTPUT)
FEATURES
• Bit organization
- 512K x 8 (byte mode)
- 256K x 16 (word mode)
• Fast access time
- Random access: 100ns
• Current
- Operating: 30mA
- Standby: 20uA
• Supply voltage
- 3.3V±10%
• Package
- 40 pin SOP (500 mil)
- 40 pin PDIP (600 mil)
ORDER INFORMATION
Part No.
MX23L4100MC-10
MX23L4100MC-12
MX23L4100MC-15
MX23L4100PC-10
MX23L4100PC-12
MX23L4100PC-15
Access Time
100ns
120ns
150ns
100ns
120ns
150ns
Package
40 pin SOP
40 pin SOP
40 pin SOP
40 pin PDIP
40 pin PDIP
40 pin PDIP
PIN CONFIGURATION
40 SOP
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
VSS
OE
D0
D8
D1
D9
D2
D10
D3
D11
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
VSS
D15/A-1
D7
D14
D6
D13
D5
D12
D4
VCC
PIN DESCRIPTION
Symbol
A0~A17
D0~D14
CE
OE
Byte
VCC
VSS
NC
Pin Function
Address Inputs
Data Outputs
Chip Enable Input
Output Enable Input
Word/ Byte Mode Selection
Power Supply Pin
Ground Pin
No Connection
MX23L4100
MODE SELECTION
CE OE Byte D15/A-1 D0~D7 D8~D15 Mode
Power
Stand-by
Active
Active
Active
40 PDIP
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
VSS
OE
D0
D8
D1
D9
D2
D10
D3
D11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
VSS
D15/A-1
D7
D14
D6
D13
D5
D12
D4
VCC
H
L
L
L
X
H
L
L
X
X
H
L
X
X
Output
Input
High Z
High Z
D0~D7
High Z
High Z
High Z
-
-
Byte
D0~D7 D8~D15 Word
P/N:PM0344
MX23L4100
REV. 1.4, JUL. 16, 2001
1
MX23L4100
BLOCK DIAGRAM
A0/(A-1)
A17
CE
BYTE
OE
Address
Buffer
Memory
Array
Sense
Amplifier
Word/
Byte
Output
Buffer
D0
D15/(D7)
ABSOLUTE MAXIMUM RATINGS
Item
Voltage on any Pin Relative to VSS
Ambient Operating Temperature
Storage Temperature
Symbol
VIN
Topr
Tstg
Ratings
-0.8V to VCC+2.0V (Note)
0° to 70°
C
C
-65° to 125°
C
C
Note: Minimum DC voltage on input or I/O pins is -0.5V.
During voltage transitions, inputs may undershoot VSS
to -0.8V for periods of up to 20ns. Maximum DC voltage
on input or I/O pins is VCC+0.5V. During voltage transi-
tions, input may overshoot VCC to VCC+2.0V for peri-
ods of up to 20ns.
DC CHARACTERISTICS
(Ta = 0°C ~ 70°C, VCC = 3.3V±10%)
Item
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage Current
Operating Current (CE toggle)
Standby Current (TTL)
Standby Current (CMOS)
Input Capacitance
Output Capacitance
Symbol
VOH
VOL
VIH
VIL
ILI
ILO
ICC1
ISTB1
ISTB2
CIN
COUT
MIN.
2.4V
-
2.2V
-0.3V
-
-
-
-
-
-
-
MAX.
-
0.4V
VCC+0.3V
0.8V
5uA
5uA
30mA
1mA
20uA
10pF
10pF
Conditions
IOH = -0.4mA
IOL = 1.6mA
0V, VCC
0V, VCC
tRC=100ns, all output open
CE = VIH
CE > VCC - 0.2V
Ta = 25° f = 1MHZ
C,
Ta = 25° f = 1MHZ
C,
P/N:PM0344
REV. 1.4, JUL. 16, 2001
2
MX23L4100
AC CHARACTERISTICS
(Ta = 0°C ~ 70°C, VCC = 3.3V±10%)
Item
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Time
Output Hold After Address
Output High Z Delay
Symbol
tRC
tAA
tACE
tOE
tOH
tHZ
23L4100-10
MIN.
MAX.
100ns -
-
-
-
-
-
100ns
100ns
50ns
0ns
20ns
23L4100-12
MIN.
MAX.
120ns
-
-
-
-
-
-
120ns
120ns
60ns
0ns
20ns
23L4100-15
MIN.
MAX.
150ns -
-
-
-
-
-
150ns
150ns
70ns
0ns
20ns
Note:Output high-impedance delay (tHZ) is measured
from OE or CE going high, and this parameter guaran-
teed by design over the full voltage and temperature op-
erating range - not tested.
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input Timing Level
Output Timing Level
Output Load
0.4V~2.4V
10ns
1.4V
1.4V
See Figure
IOH (load)=-0.4mA
DOUT
IOL (load)=1.6mA
C<100pF
Note:No output loading is present in tester load board.
Active loading is used and under software programming control.
TIMING DIAGRAM
ACCESS TIMING
Output loading capacitance includes load board's and all stray capacitance.
ADD
ADD
tACE
ADD
tRC
ADD
CE
tOE
OE
tAA
tOH
tHZ
DATA
VALID
VALID
VALID
P/N:PM0344
REV. 1.4, JUL. 16, 2001
3
MX23L4100
PACKAGE INFORMATION
40-PIN PLASTIC DIP (600 mil)
P/N:PM0344
REV. 1.4, JUL. 16, 2001
4
MX23L4100
40-PIN PLASTIC SOP
P/N:PM0344
REV. 1.4, JUL. 16, 2001
5