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MUN5313DW1T1

Description
PRE-BIASED DIGITAL TRANSISTOR,50V V(BR)CEO,100MA I(C),SOT-363
CategoryDiscrete semiconductor    The transistor   
File Size367KB,13 Pages
ManufacturerLRC
Websitehttp://www.lrc.cn
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MUN5313DW1T1 Overview

PRE-BIASED DIGITAL TRANSISTOR,50V V(BR)CEO,100MA I(C),SOT-363

MUN5313DW1T1 Parametric

Parameter NameAttribute value
MakerLRC
package instruction,
Reach Compliance Codeunknow
Maximum collector current (IC)0.1 A
Minimum DC current gain (hFE)80
Number of components2
Polarity/channel typePNP
Maximum power dissipation(Abs)0.385 W
surface mountYES
Transistor component materialsSILICON
LESHAN RADIO COMPANY, LTD.
Dual Bias Resistor Transistors
NPN and PNP Silicon Surface Mount
Transistors with Monolithic Bias
Resistor Network
The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias network
consisting of two resistors; a series base resistor and a base–emitter resistor. These digital tran-
sistors are designed to replace a single device and its external resistor bias network. The BRT
eliminates these individual components by integrating them into a single device. In the
MUN5311DW1T1 series, two complementary BRT devices are housed in the SOT–363 package
which is ideal for low power surface mount applications where board space is at a premium.
• Simplifies Circuit Design
• Reduces Board Space
• Reduces Component Count
• Available in 8 mm, 7 inch/3000 Unit Tape and Reel
MUN5311DW1T1
Series
6
5
4
1
2
3
SOT-363
CASE 419B STYLE1
MAXIMUM RATINGS
(T
A
= 25°C unless otherwise noted, common for Q
1
6
5
4
and Q
2
, – minus sign for Q
1
(PNP) omitted)
Rating
Collector-Base Voltage
Collector-Emitter Voltage
Collector Current
THERMAL CHARACTERISTICS
Characteristic
(One Junction Heated)
Total Device Dissipation
T
A
= 25°C
Derate above 25°C
Thermal Resistance –
Junction-to-Ambient
Characteristic
(Both Junctions Heated)
Total Device Dissipation
T
A
= 25°C
Derate above 25°C
Thermal Resistance –
Junction-to-Ambient
Thermal Resistance –
Junction-to-Lead
Junction and Storage
Temperature
1. FR–4 @ Minimum Pad
Symbol Value
V
CBO
50
V
CEO
50
I
C
100
Unit
Vdc
Vdc
mAdc
Q
2
R
2
R
1
1
2
R
1
R
2
Q
1
3
Symbol
P
D
Max
187 (Note 1.)
256 (Note 2.)
1.5 (Note 1.)
2.0 (Note 2.)
Unit
mW
mW/°C
°C/W
MARKING DIAGRAM
6
5
4
XX
1
2
3
R
θJA
670 (Note 1.)
490 (Note 2.)
xx = Device Marking
=
(See Page 2)
Symbol
P
D
Max
250 (Note 1.)
385 (Note 2.)
2.0 (Note 1.)
3.0 (Note 2.)
493 (Note 1.)
325 (Note 2.)
188 (Note 1.)
208 (Note 2.)
–55 to +150
Unit
mW
mW/°C
°C/W
°C/W
°C
DEVICE MARKING
INFORMATION
See specific marking information in
the device marking table on page 2 of
this data sheet.
R
θJA
R
θJL
T
J
, T
stg
2. FR–4 @ 1.0 x 1.0 inch Pad
MUN5311dw–1/13

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Description PRE-BIASED DIGITAL TRANSISTOR,50V V(BR)CEO,100MA I(C),SOT-363 PRE-BIASED DIGITAL TRANSISTOR,50V V(BR)CEO,100MA I(C),SOT-363 PRE-BIASED DIGITAL TRANSISTOR,50V V(BR)CEO,100MA I(C),SOT-363 PRE-BIASED DIGITAL TRANSISTOR,50V V(BR)CEO,100MA I(C),SOT-363 PRE-BIASED DIGITAL TRANSISTOR,50V V(BR)CEO,100MA I(C),SOT-363 PRE-BIASED DIGITAL TRANSISTOR,50V V(BR)CEO,100MA I(C),SOT-363 PRE-BIASED DIGITAL TRANSISTOR,50V V(BR)CEO,100MA I(C),SOT-363 PRE-BIASED DIGITAL TRANSISTOR,50V V(BR)CEO,100MA I(C),SOT-363
Maker LRC - LRC LRC LRC LRC LRC LRC
Reach Compliance Code unknow - unknow unknow unknow unknown unknow unknow
Maximum collector current (IC) 0.1 A - 0.1 A 0.1 A 0.1 A 0.1 A 0.1 A 0.1 A
Minimum DC current gain (hFE) 80 - 80 15 8 160 160 60
Number of components 2 - 2 2 2 2 2 2
Polarity/channel type PNP - PNP PNP PNP PNP PNP PNP
Maximum power dissipation(Abs) 0.385 W - 0.385 W 0.385 W 0.385 W 0.385 W 0.385 W 0.385 W
surface mount YES - YES YES YES YES YES YES
Transistor component materials SILICON - SILICON SILICON SILICON SILICON SILICON SILICON
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