MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MTSF3N02HD/D
Designer's
™
Data Sheet
Medium Power Surface Mount Products
MTSF3N02HD
Motorola Preferred Device
TMOS Single N-Channel
Field Effect Transistor
Micro8™ devices are an advanced series of power MOSFETs
which utilize Motorola’s High Cell Density HDTMOS process to
achieve lowest possible on–resistance per silicon area. They are
capable of withstanding high energy in the avalanche and commuta-
tion modes and the drain–to–source diode has a very low reverse
recovery time. Micro8™ devices are designed for use in low voltage,
high speed switching applications where power efficiency is important.
Typical applications are dc–dc converters, and power management in
portable and battery powered products such as computers, printers,
cellular and cordless phones. They can also be used for low voltage
motor controls in mass storage products such as disk drives and tape
drives. The avalanche energy is specified to eliminate the guesswork
in designs where inductive loads are switched and offer additional
safety margin against unexpected voltage transients.
•
Miniature Micro8 Surface Mount Package — Saves Board Space
•
Extremely Low Profile (<1.1mm) for thin applications such as
PCMCIA cards
•
Ultra Low RDS(on) Provides Higher Efficiency and Extends Bat-
tery Life
•
Logic Level Gate Drive — Can Be Driven by Logic ICs
•
Diode Is Characterized for Use In Bridge Circuits
•
Diode Exhibits High Speed, With Soft Recovery
•
IDSS Specified at Elevated Temperature
•
Avalanche Energy Specified
•
Mounting Information for Micro8 Package Provided
SINGLE TMOS
POWER MOSFET
4.0 AMPERES
20 VOLTS
RDS(on) = 0.040 OHM
™
D
CASE 846A–02, Style 1
Micro8
G
S
Source
Source
Source
Gate
1
2
3
4
8
7
6
5
Drain
Drain
Drain
Drain
Top View
DEVICE MARKING
AC
Device
MTSF3N02HDR2
ORDERING INFORMATION
Reel Size
13″
Tape Width
12 mm embossed tape
Quantity
4000 units
Designer’s Data for “Worst Case” Conditions
— The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Preferred devices
are Motorola recommended choices for future use and best overall value.
HDTMOS is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc. Micro8 is a registered trademark of International
Rectifier. Thermal Clad is a trademark of the Bergquist Company.
REV 4
©
Motorola TMOS Power MOSFET Transistor Device Data
Motorola, Inc. 1997
1
MTSF3N02HD
MAXIMUM RATINGS
(TJ = 25°C unless otherwise noted)
Rating
Drain–to–Source Voltage
Drain–to–Gate Voltage (RGS = 1.0 MΩ)
Gate–to–Source Voltage — Continuous
1 inch SQ.
FR–4 or G–10 PCB
Figure 1 below
Thermal Resistance — Junction to Ambient
Total Power Dissipation @ TA = 25°C
Linear Derating Factor
Drain Current — Continuous @ TA = 25°C
Continuous @ TA = 70°C
Pulsed Drain Current (1)
Thermal Resistance — Junction to Ambient
Total Power Dissipation @ TA = 25°C
Linear Derating Factor
Drain Current — Continuous @ TA = 25°C
Continuous @ TA = 70°C
Pulsed Drain Current (1)
Symbol
VDSS
VDGR
VGS
RTHJA
PD
ID
ID
IDM
RTHJA
PD
ID
ID
IDM
TJ, Tstg
Max
20
20
±
8.0
70
1.79
14.29
6.1
4.9
49
160
0.78
6.25
4.0
3.2
32
– 55 to 150
Unit
V
V
V
°C/W
Watts
mW/°C
A
A
A
°C/W
Watts
mW/°C
A
A
A
°C
Steady State
Minimum
FR–4 or G–10 PCB
Figure 2 below
Steady State
Operating and Storage Temperature Range
(1) Repetitive rating; pulse width limited by maximum junction temperature.
Figure 1. 1.0 Inch Square FR–4 or G–10 PCB
Figure 2. Minimum FR–4 or G–10 PCB
2
Motorola TMOS Power MOSFET Transistor Device Data
MTSF3N02HD
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250
µAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(VDS = 16 Vdc, VGS = 0 Vdc)
(VDS = 16 Vdc, VGS = 0 Vdc, TJ = 125°C)
Gate–Body Leakage Current (VGS =
±
8.0 Vdc, VDS = 0 Vdc)
ON CHARACTERISTICS(1)
Gate Threshold Voltage
(VDS = VGS, ID = 250
µAdc)
Threshold Temperature Coefficient (Negative)
Static Drain–to–Source On–Resistance
(VGS = 4.5 Vdc, ID = 3.8 Adc)
(VGS = 2.7 Vdc, ID = 1.9 Adc)
(Cpk
≥
2.0)
(3)
VGS(th)
0.7
—
(Cpk
≥
2.0)
(3)
RDS(on)
—
—
(1)
gFS
4.0
30
40
7.5
40
50
—
Mhos
0.98
2.65
1.1
—
Vdc
mV/°C
mΩ
(Cpk
≥
2.0)
(1) (3)
V(BR)DSS
20
—
IDSS
—
—
IGSS
—
—
—
—
1.0
25
100
nAdc
—
16
—
—
Vdc
mV/°C
µAdc
Symbol
Min
Typ
Max
Unit
Forward Transconductance (VDS = 10 Vdc, ID = 1.9 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS(2)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Gate Charge
Ciss
(VDS = 15 Vdc, VGS = 0 Vdc,
Vdc
Vdc
f = 1.0 MHz)
Coss
Crss
—
—
—
475
255
110
—
—
—
pF
td(on)
(
(VDS = 10 Vd , ID = 3 8 Ad ,
Vdc,
3.8 Adc,
VGS = 4.5 Vdc, RG = 6
Ω)
(1)
tr
td(off)
tf
td(on)
(
(VDD = 10 Vd , ID = 1.9 Adc,
Vdc,
1 9 Ad ,
VGS = 2.7 Vdc, RG = 6
Ω)
(1)
tr
td(off)
tf
QT
(
(VDS = 16 Vd , ID = 3 8 Ad ,
Vdc,
3.8 Adc,
VGS = 4.5 Vdc)
Q1
Q2
Q3
—
—
—
—
—
—
—
—
—
—
—
—
9.5
45
50
62
19
130
38
47
12
1.0
5.0
3.5
—
—
—
—
—
—
—
—
17
—
—
—
ns
ns
nC
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
(IS = 3.8 Adc, VGS = 0 Vdc) (1)
(IS = 3.8 Adc, VGS = 0 Vdc, TJ = 125°C)
VSD
—
—
trr
(IS = 3 8 Adc VGS = 0 Vdc,
3.8 Adc,
Vdc
dIS/dt = 100 A/µs) (1)
Reverse Recovery Storage Charge
(1) Pulse Test: Pulse Width
≤
300
µs,
Duty Cycle
≤
2%.
(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.
Max limit – Typ
Cpk =
3 x SIGMA
ta
tb
QRR
—
—
—
—
0.83
0.68
46
23
23
0.05
1.0
—
—
—
—
—
µC
ns
Vdc
Reverse Recovery Time
Motorola TMOS Power MOSFET Transistor Device Data
3
MTSF3N02HD
TYPICAL ELECTRICAL CHARACTERISTICS
8
7
I D , DRAIN CURRENT (AMPS)
6
5
4
3
2
1
0
0
0.4
0.8
1.2
1.6
2
1.5 V
I D , DRAIN CURRENT (AMPS)
VGS = 10 V
4.5 V
2.9 V
2.5 V
2.3 V
2.1 V
TJ = 25°C
1.9 V
8
7
6
5
4
3
2
25°C
1
0
1
1.2
1.4
100°C
1.6
1.8
2
TJ = –55°C
VDS
≥
10 V
1.7 V
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
Figure 3. On–Region Characteristics
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
Figure 4. Transfer Characteristics
0.06
VGS = 3.8 V
TJ = 25°C
0.05
0.06
TJ = 25°C
0.05
VGS = 2.7 V
4.5 V
0.03
0.04
0.04
0.03
0.02
0.02
0.01
0
2
4
6
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
8
0.01
0
1
2
3
4
5
6
7
8
ID, DRAIN CURRENT (AMPS)
Figure 5. On–Resistance versus
Gate–to–Source Voltage
RDS(on), DRAIN–TO–SOURCE RESISTANCE (NORMALIZED)
Figure 6. On–Resistance versus Drain Current
and Gate Voltage
2.0
VGS = 4.5 V
ID = 1.9 A
I DSS , LEAKAGE (nA)
1.5
1000
VGS = 0 V
100
100°C
10
TJ = 125°C
1.0
0.5
1
25°C
0
– 50
0.1
– 25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (°C)
0
4
8
12
16
20
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7. On–Resistance Variation
with Temperature
Figure 8. Drain–to–Source Leakage Current
versus Voltage
4
Motorola TMOS Power MOSFET Transistor Device Data
MTSF3N02HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculat-
ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a resis-
tive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off–state condition when cal-
culating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 11) shows how typical switching performance
is affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.
2500
Ciss
2000
C, CAPACITANCE (pF)
Crss
1500
TJ = 25°C
VGS = 0 V
1000
Ciss
Coss
8
4
VGS
0
Crss
4
VDS
8
12
16
20
500
0
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 9. Capacitance Variation
Motorola TMOS Power MOSFET Transistor Device Data
5
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