MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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TMOS E-FET.
™
High Energy Power FET
D2PAK-SL Straight Lead
N–Channel Enhancement–Mode Silicon Gate
This high voltage MOSFET uses an advanced termination
scheme to provide enhanced voltage–blocking capability without
degrading performance over time. In addition, this advanced TMOS
E–FET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
drain–to–source diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
•
Robust High Voltage Termination
•
Avalanche Energy Specified
•
Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
•
Diode is Characterized for Use in Bridge Circuits
•
IDSS and VDS(on) Specified at Elevated Temperature
•
Short Heatsink Tab Manufactured — Not Sheared
•
Specially Designed Leadframe for Maximum Power Dissipation
MTB4N80E1
Motorola Preferred Device
TMOS POWER FET
4.0 AMPERES
800 VOLTS
RDS(on) = 3.0 OHM
®
D
G
CASE 418C–01, Style 2
D2PAK–SL
S
MAXIMUM RATINGS
(TC = 25°C unless otherwise noted)
Rating
Drain–Source Voltage
Drain–Gate Voltage (RGS = 1.0 MΩ)
Gate–Source Voltage — Continuous
Gate–Source Voltage
— Non–Repetitive (tp
≤
10 ms)
Drain Current — Continuous
Drain Current
— Continuous @ 100°C
Drain Current
— Single Pulse (tp
≤
10
µs)
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TA = 25°C, when mounted with the minimum recommended pad size
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 100 Vdc, VGS = 10 Vdc, IL = 8.0 Apk, L = 10 mH, RG = 25
Ω)
Thermal Resistance — Junction to Case
Thermal Resistance
— Junction to Ambient
Thermal Resistance
— Junction to Ambient, when mounted with the minimum recommended pad size
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
Symbol
VDSS
VDGR
VGS
VGSM
ID
ID
IDM
PD
Value
800
800
±
20
±
40
4.0
2.9
12
125
1.0
2.5
– 55 to 150
320
1.0
62.5
50
260
Unit
Vdc
Vdc
Vdc
Vpk
Adc
Apk
Watts
W/°C
Watts
°C
mJ
°C/W
TJ, Tstg
EAS
R
θJC
R
θJA
R
θJA
TL
°C
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
E–FET is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred
devices are Motorola recommended choices for future use and best overall value.
©
Motorola TMOS Power MOSFET Transistor Device Data
Motorola, Inc. 1997
1
MTB4N80E1
ELECTRICAL CHARACTERISTICS
(TJ = 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250
µAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(VDS = 800 Vdc, VGS = 0 Vdc)
(VDS = 800 Vdc, VGS = 0 Vdc, TJ = 125°C)
Gate–Body Leakage Current (VGS =
±
20 Vdc, VDS = 0)
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250
µAdc)
Temperature Coefficient (Negative)
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 2.0 Adc)
Drain–Source On–Voltage (VGS = 10 Vdc)
(ID = 4.0 Adc)
(ID = 2.0 Adc, TJ = 125°C)
Forward Transconductance (VDS = 15 Vdc, ID = 2.0 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Gate Charge
(See Figure 8)
(
(VDS = 400 Vdc, ID = 4 0 Ad ,
Vd ,
4.0 Adc,
VGS = 10 Vdc)
4.0 Adc,
(VDD = 400 Vdc, ID = 4 0 Ad
Vd
VGS = 10 Vdc
Vdc,
RG = 9.1
Ω)
)
td(on)
tr
td(off)
tf
QT
Q1
Q2
Q3
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage (1)
(IS = 4.0 Adc, VGS = 0 Vdc)
(IS = 4.0 Adc, VGS = 0 Vdc, TJ = 125°C)
VSD
—
—
trr
Vd ,
(
(IS = 4 0 Ad , VGS = 0 Vdc,
4.0 Adc,
dIS/dt = 100 A/µs)
Reverse Recovery Stored Charge
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
(1) Pulse Test: Pulse Width
≤
300
µs,
Duty Cycle
≤
2%.
(2) Switching characteristics are independent of operating junction temperature.
LD
LS
—
—
4.5
7.5
—
—
nH
nH
ta
tb
QRR
—
—
—
—
0.812
0.7
557
100
457
2.33
1.5
—
—
—
—
—
µC
ns
Vdc
—
—
—
—
—
—
—
—
13
36
40
30
36
7.0
16.5
12
30
90
80
75
80
—
—
—
nC
ns
(VDS = 25 Vdc, VGS = 0 Vdc,
Vdc
Vdc
f = 1.0 MHz)
Ciss
Coss
Crss
—
—
—
1320
187
72
2030
400
160
pF
VGS(th)
2.0
—
RDS(on)
VDS(on)
—
—
gFS
2.0
8.24
—
4.3
12
10
—
mhos
—
3.0
7.0
1.95
4.0
—
3.0
Vdc
mV/°C
Ohm
Vdc
V(BR)DSS
800
—
IDSS
—
—
IGSS
—
—
—
—
10
100
100
nAdc
—
1.02
—
—
Vdc
mV/°C
µAdc
Symbol
Min
Typ
Max
Unit
Reverse Recovery Time
(See Figure 14)
2
Motorola TMOS Power MOSFET Transistor Device Data
MTB4N80E1
TYPICAL ELECTRICAL CHARACTERISTICS
8
7
I D , DRAIN CURRENT (AMPS)
6
5
4
3
2
1
0
0
2
4
4V
6
8
10
12
14
16
18
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
20
5V
TJ = 25°C
I D , DRAIN CURRENT (AMPS)
VGS = 10 V
6V
8
7
6
5
4
25°C
3
2
1
0
2.0
2.4
TJ = –55°C
100°C
VDS
≥
10 V
2.8
3.2
3.6
4.0
4.4
4.8
5.2
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
5.6
Figure 1. On–Region Characteristics
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
Figure 2. Transfer Characteristics
4.6
VGS = 10 V
3.8
TJ = 100°C
2.6
2.5
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1
2
3
4
5
6
ID, DRAIN CURRENT (AMPS)
7
8
VGS = 10 V
15 V
TJ = 25°C
3.0
25°C
2.2
1.4
– 55°C
0.6
1
2
5
3
4
6
ID, DRAIN CURRENT (AMPS)
7
8
Figure 3. On–Resistance versus Drain Current
and Temperature
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
RDS(on) , DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
2.2
VGS = 10 V
ID = 2 A
10000
VGS = 0 V
TJ = 125°C
1000
I DSS , LEAKAGE (nA)
100°C
1.8
1.4
100
1.0
10
25°C
0.6
0.2
–50
1
–25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
150
0
100
300
500
600
200
400
700
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
800
Figure 5. On–Resistance Variation with
Temperature
Figure 6. Drain–To–Source Leakage
Current versus Voltage
Motorola TMOS Power MOSFET Transistor Device Data
3
MTB4N80E1
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculat-
ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a resis-
tive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off–state condition when cal-
culating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.
2800
2400
C, CAPACITANCE (pF)
2000
1600
1200
800
400
Crss
0
10
5
VGS
0
VDS
5
10
15
20
25
Coss
Crss
Ciss
Ciss
VDS = 0 V
VGS = 0 V
TJ = 25°C
10000
VGS = 0 V
1000
C, CAPACITANCE (pF)
Ciss
TJ = 25°C
100
Coss
10
Crss
1
10
100
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
1000
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7a. Capacitance Variation
Figure 7b. High Voltage Capacitance
Variation
4
Motorola TMOS Power MOSFET Transistor Device Data
MTB4N80E1
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
10
QT
8
VGS
6
Q1
Q2
300
400
500
VDS , DRAIN–TO–SOURCE VOLTAGE (VOLTS)
1000
VDD = 400 V
ID = 4 A
VGS = 10 V
TJ = 25°C
t, TIME (ns)
100
tf
td(off)
tr
4
ID = 4 A
TJ = 25°C
200
2
Q3
0
0
6
12
18
24
QG, TOTAL GATE CHARGE (nC)
VDS
100
30
0
36
10
1
td(on)
10
RG, GATE RESISTANCE (OHMS)
100
Figure 8. Gate–To–Source and Drain–To–Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
4.0
3.6
I S , SOURCE CURRENT (AMPS)
3.2
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0
0.50
0.54
0.58
0.62
0.66
0.70
0.74
0.78
0.82
VGS = 0 V
TJ = 25°C
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is for-
ward biased. Curves are based upon maximum peak junc-
tion temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance–Gener-
al Data and Its Use.”
Switching between the off–state and the on–state may tra-
verse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10
µs.
In addition the total power aver-
aged over a complete switching cycle must not exceed
(TJ(MAX) – TC)/(R
θJC
).
A Power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For reli-
able operation, the stored energy from circuit inductance dis-
sipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a con-
stant. The energy rating decreases non–linearly with an in-
crease of peak current in avalanche and peak junction
temperature.
Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous cur-
rent (ID), in accordance with industry custom. The energy rat-
ing must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at cur-
rents below rated continuous ID can safely be assumed to
equal the values indicated.
Motorola TMOS Power MOSFET Transistor Device Data
5
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