TLP5702
Photocouplers
GaAℓAs Infrared LED & Photo IC
TLP5702
1. Applications
•
•
•
•
•
Induction Cooktop and Home Appliances
Industrial Inverters
Air Conditioner Inverters
MOSFET Gate Drivers
IGBT Gate Drivers
2. General
The TLP5702 is a photocoupler in a 6-pin SO6L package that consists of a GaAℓAs infrared light-emitting diode
(LED) optically coupled to an integrated high-gain, high-speed photodetector IC chip. It provides guaranteed
performance and specifications at temperature up to 110
.
The TLP5702 is physically smaller / thinner than the one in an 8-pin DIP package and compliant with international
safety standards for reinforced insulation. It thus provides a smaller footprint solution for applications that
require safety standard certification. An internal noise shield provides a guaranteed common-mode transient
immunity of
±20
kV/µs.
The TLP5702 is ideal for small to medium class IGBT and power MOSFET gate drive.
3. Features
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
Buffer logic type (totem pole output)
Output peak current:
±2.5
A (max)
Operating temperature: -40 to 110
Supply current: 3.0 mA (max)
Supply voltage: 15 to 30 V
Threshold input current: 5 mA (max)
Propagation delay time: t
pHL
/t
pLH
= 200 ns (max)
Common-mode transient immunity:
±20
kV/µs (min)
Isolation voltage: 5000 Vrms (min)
UL-approved: UL1577, File No.E67349
cUL-approved: CSA Component Acceptance Service No.5A File No.E67349
VDE-approved: EN60747-5-5, EN60065, EN60950-1, EN 62368-1 (Note 1)
CQC-approved: GB4943.1, GB8898
Note 1: When a VDE approved type is needed, please designate the Option (D4)
(D4).
(10) Safety standards
Start of commercial production
©2015 Toshiba Corporation
1
2014-01
2017-03-17
Rev.4.0
TLP5702
4. Packaging (Note)
TLP5702
TLP5702(LF4)
11-4N1A
11-4N101A
Note:
Lead-formed product: (LF4)
5. Pin Assignment
1: Anode
2: N.C.
3: Cathode
4: GND
5: V
O
(Output)
6: V
CC
6. Internal Circuit (Note)
Note:
A 0.1-µF bypass capacitor must be connected between pin 6 and pin 4.
©2015 Toshiba Corporation
2
2017-03-17
Rev.4.0
TLP5702
7. Principle of Operation
7.1. Truth Table
Input
H
L
LED
ON
OFF
M1
ON
OFF
M2
OFF
ON
Output
H
L
7.2. Mechanical Parameters
Characteristics
Height
Creepage distances
Clearance distances
Internal isolation thickness
Size
2.3 (max)
8.0 (min)
8.0 (min)
0.4 (min)
Unit
mm
8. Absolute Maximum Ratings (Note) (Unless otherwise specified, T
a
= 25
)
Characteristics
LED
Input forward current
Input forward current derating
Peak transient input forward
current
Peak transient input forward
current derating
Input reverse voltage
Input power dissipation
Input power dissipation
derating
Detector Peak high-level output current
Peak low-level output current
Output voltage
Supply voltage
Output power dissipation
Output power dissipation
derating
Common Operating temperature
Storage temperature
Lead soldering temperature
Isolation voltage
(10 s)
AC, 60 s,
R.H.
≤
60 %
(T
a
≥
85
)
(T
a
≥
85
)
(T
a
= -40 to 110
)
(T
a
= -40 to 110
)
(T
a
≥
85
)
(T
a
≥
105
)
Symbol
I
F
∆I
F
/∆T
a
I
FPT
∆I
FPT
/∆T
a
V
R
P
D
∆P
D
/∆T
a
I
OPH
I
OPL
V
O
V
CC
P
O
∆P
O
/∆T
a
T
opr
T
stg
T
sol
BV
S
(Note 3)
(Note 4)
(Note 2)
(Note 2)
(Note 1)
Note
Rating
20
-1
1
-25
5
40
-1.0
-2.5
+2.5
35
35
160
-4.0
-40 to 110
-55 to 125
260
5000
Vrms
mW
mW/
V
Unit
mA
mA/
A
mA/
V
mW
mW/
A
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even
if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum
ratings. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability
Handbook ("Handling Precautions"/"Derating Concept and Methods") and individual reliability data (i.e.
reliability test report and estimated failure rate, etc).
Note 1: Pulse width (PW)
≤
1
µs,
300 pps
Note 2: Exponential waveform. Pulse width
≤
0.3
µs,
f
≤
15 kHz
Note 3:
≥
2 mm below seating plane.
Note 4: This device is considered as a two-terminal device: Pins 1, 2 and 3 are shorted together, and pins 4, 5 and 6
are shorted together.
Note:
©2015 Toshiba Corporation
3
2017-03-17
Rev.4.0
TLP5702
9. Recommended Operating Conditions (Note)
Characteristics
Input on-state current
Input off-state voltage
Supply voltage
Peak high-level output current
Peak low-level output current
Operating frequency
Symbol
I
F(ON)
V
F(OFF)
V
CC
I
OPH
I
OPL
f
(Note 2)
(Note 2)
(Note 3)
Note
(Note 1)
Min
6.5
0
15
Typ.
Max
10
0.8
30
-2.0
+2.0
50
kHz
A
Unit
mA
V
The recommended operating conditions are given as a design guide necessary to obtain the intended
performance of the device. Each parameter is an independent value. When creating a system design using
this device, the electrical characteristics specified in this datasheet should also be considered.
Note: A ceramic capacitor (0.1
µF)
should be connected between pin 6 (Vcc) and pin 4 (GND) to stabilize the operation
of a high-gain linear amplifier. Otherwise, this photocoupler may not switch properly. The bypass capacitor
should be placed within 1 cm of each pin.
Note 1: The rise and fall times of the input on-current should be less than 0.5
µs.
Note 2: Exponential waveform. I
OPH
≥
-2.0 A (≤ 0.3
µs),
I
OPL
≤
2.0 A (≤ 0.3
µs),
VCC = 15 V, T
a
= 110
Note 3: Denotes the operating range, not the recommended operating condition.
Note:
10. Electrical Characteristics (Note) (Unless otherwise specified, T
a
= -40 to 110
)
Characteristics
Input forward voltage
Input forward voltage
temperature coefficient
Input reverse current
Input capacitance
Peak high-level output current
Symbol
V
F
∆V
F
/∆T
a
I
R
C
t
I
OPH
(Note 1)
Fig.
12.1.1
Note
Test
Circuit
Test Condition
I
F
= 10 mA, T
a
= 25
I
F
= 10 mA
V
R
= 5 V, T
a
= 25
V = 0 V, f = 1 MHz, T
a
= 25
I
F
= 5 mA, V
CC
= 15 V,
V
6-5
= -3.5 V
I
F
= 5 mA, V
CC
= 15 V,
V
6-5
= -7 V
Peak low-level output current
I
OPL
(Note 1)
Fig.
12.1.2
I
F
= 0 mA, V
CC
= 15 V,
V
5-4
= 2.5 V
I
F
= 0 mA, V
CC
= 15 V,
V
5-4
= 7 V
High-level output voltage
Low-level output voltage
High-level supply current
Low-level supply current
Threshold input current (L/H)
Threshold input voltage (H/L)
Supply voltage
UVLO threshold voltage
UVLO hysteresis
V
OH
V
OL
I
CCH
I
CCL
I
FLH
V
FHL
V
CC
V
UVLO+
V
UVLO-
UVLO
HYS
Fig.
12.1.3
Fig.
12.1.4
Fig.
12.1.5
Fig.
12.1.6
I
F
= 5 mA, R
L
= 200
Ω,
V
CC1
= +15 V, V
EE1
= -15 V
V
F
= 0.8 V, R
L
= 200
Ω,
V
CC1
= +15 V, V
EE1
= -15 V
I
F
= 10 mA, V
CC
= 30 V,
V
O
= Open
I
F
= 0 mA, V
CC
= 30 V,
V
O
= Open
V
CC
= 15 V, V
O
> 1 V
V
CC
= 15 V, V
O
< 1 V
I
F
= 5 mA, V
O
> 2.5 V
I
F
= 5 mA, V
O
< 2.5 V
Min
1.45
1.0
2.0
11.0
0.8
15
11.0
9.5
Typ.
1.55
-2.0
60
-1.6
1.6
13.7
-14.9
1.5
1.5
1.0
12.5
11.0
1.5
Max
1.70
10
-1.0
-2.0
-12.5
3.0
3.0
5
30
13.5
12.0
V
mA
V
Unit
V
mV/
µA
pF
A
Note:
Note:
All typical values are at T
a
= 25
.
This device is designed for low power consumption, making it more sensitive to ESD than its predecessors.
Extra care should be taken in the design of circuitry and pc board implementation to avoid ESD problems.
Note 1: I
O
application time
≤
50
µs;
single pulse.
©2015 Toshiba Corporation
4
2017-03-17
Rev.4.0
TLP5702
11. Isolation Characteristics (Unless otherwise specified, T
a
= 25
)
Characteristics
Total capacitance (input to
output)
Isolation resistance
Isolation voltage
Symbol
C
S
R
S
BV
S
Note
Test Conditions
Min
1
×
10
12
5000
Typ.
1.0
10
14
10000
10000
Max
Vdc
Unit
pF
Ω
Vrms
(Note 1) V
S
= 0 V, f = 1 MHz
(Note 1) V
S
= 500 V, R.H.
≤
60 %
(Note 1) AC, 60 s
AC, 1 s in oil
DC, 60 s in oil
Note 1: This device is considered as a two-terminal device: Pins 1, 2 and 3 are shorted together, and pins 4, 5 and 6
are shorted together.
12. Switching Characteristics (Note) (Unless otherwise specified, T
a
= -40 to 110
)
Characteristics
Propagation delay time
(L/H)
Propagation delay time
(H/L)
Rise time
Fall time
Pulse width distortion
Propagation delay skew
(device to device)
Common-mode transient
immunity at output high
Common-mode transient
immunity at output low
Symbol
t
pLH
t
pHL
t
r
t
f
|t
pHL
-t
pLH
|
t
psk
CM
H
Note
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 2)
Fig.
12.1.8
V
CM
= 1000 V
p-p
, I
F
= 5 mA,
V
CC
= 30 V, T
a
= 25
,
V
O(min)
= 26 V
V
CM
= 1000 V
p-p
, I
F
= 0 mA,
V
CC
= 30 V, T
a
= 25
,
V
O(max)
= 1 V
Test
Circuit
Fig.
12.1.7
Test Condition
I
F
= 0
→
5 mA, V
CC
= 30 V,
R
g
= 20
Ω,
C
g
= 10 nF
I
F
= 5
→
0 mA, V
CC
= 30 V,
R
g
= 20
Ω,
C
g
= 10 nF
I
F
= 0
→
5 mA, V
CC
= 30 V,
R
g
= 20
Ω,
C
g
= 10 nF
I
F
= 5
→
0 mA, V
CC
= 30 V,
R
g
= 20
Ω,
C
g
= 10 nF
I
F
= 0
←→
5 mA, V
CC
= 30 V,
R
g
= 20
Ω,
C
g
= 10 nF
Min
50
50
-80
±20
Typ.
15
8
±25
Max
200
200
50
80
kV/µs
Unit
ns
CM
L
(Note 3)
±20
±25
Note: All typical values are at T
a
= 25
.
Note 1: Input signal (f = 25 kHz, duty = 50 %, t
r
= t
f
= 5 ns or less).
C
L
is approximately 15 pF which includes probe and stray wiring capacitance.
Note 2: CM
H
is the maximum rate of fall of the common mode voltage that can be sustained with the output voltage in
the logic high state (V
O
> 26 V).
Note 3: CM
L
is the maximum rate of rise of the common mode voltage that can be sustained with the output voltage
in the logic low state (V
O
< 1 V).
©2015 Toshiba Corporation
5
2017-03-17
Rev.4.0
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