EVAL-AD5432EB datasheet, PDF - EEWORLD Datasheet

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EVAL-AD5432EB: DescriptionSERIAL INPUT LOADING, 0.09 us SETTLING TIME, 8-BIT DAC, PDSO10; Categorysemiconductor logic; File Size910KB，24 Pages; ManufacturerADI; Websitehttps://www.analog.com

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EVAL-AD5432EB Overview

SERIAL INPUT LOADING, 0.09 us SETTLING TIME, 8-BIT DAC, PDSO10

EVAL-AD5432EB Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	10
Maximum operating temperature	125 Cel
Minimum operating temperature	-40 Cel
Maximum linear error	0.0977 %
Processing package description	3 X 5 MM, MSOP-10
state	EOL/LIFEBUY
Craftsmanship	CMOS
packaging shape	SQUARE
Package Size	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
surface mount	Yes
Terminal form	GULL WING
Terminal spacing	0.5000 mm
terminal coating	TIN LEAD
Terminal location	DUAL
Packaging Materials	PLASTIC/EPOXY
Temperature level	AUTOMOTIVE
Input format	SERIAL
Type of converter	8-BIT DAC
Input bit encoding	BINARY
Rated settling time	0.0900 us
Maximum analog output voltage	5 V
Minimum analog output voltage	0.4000 V

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8/10/12½高带½

乘法DAC，内½串行接口

AD5426/AD5432/AD5443

产品特性

2.5 V至5.5 V电源供电

50 MHz串行接口

乘法带½：10

MHz

更新速率：2.5

MSPS

INL：±1 LSB(12½DAC)

±10 V基准电压输入

½毛刺½量<

2 nV-s

扩展温度范围：−40°C至+125°C

10引脚MSOP封装

引脚兼容的8/10/12½电流输出DAC

保证单调性

四象限乘法

上电复½，具有掉电检测功½

菊花链模式

回读功½

功耗：0.4

A(典型值)

概述

AD5426/AD5432/AD5443

分别是CMOS、8/10/12½、电流

输出数模½换器(DAC)。这些器件采用2.5

V至5.5 V电源供电，

适合电池供电应用及许多其它应用。

这些DAC采用双缓冲三线式串行接口，并且与SPI、QSPI™、

MICROWIRE™及大多数DSP接口标准兼容。采用多个封装

时，还可以通过串行数据输出引脚(SDO)，将这些DAC以

菊花链½式相连。利用数据回读功½，用户可以通过SDO

引脚读取DAC寄存器的内容。上电时，内部移½寄存器和

锁存以0填充，DAC输出处于零电平。

上述器件采用CMOS亚微米工艺制造，½够提供出色的四

象限乘法特性，大信号乘法带½达10

MHz。满量程输出电

流由所½加的外部基准输入电压V

REF

决定。与外部电流至

电压精密放大器配合½用时，集成的反馈电阻R

可提供温

度跟踪和满量程电压输出。

AD5426/AD5432/AD5443

DAC采用小型、10引脚MSOP封装。

提供

EVAL-AD5443SDZ/EVAL-AD5446SDZ/EVAL-

AD5453SDZ评估板用于评估DAC性½。欲了解更多信息，

请参阅UG-327评估板用户指南。

应用

便携式电池供电应用

波½发生器

模拟处理

仪器仪表

可编程放大器和衰减器

数字控制校准

可编程滤波器和振荡器

复合视频

超声

增益、失调和电压调整

功½框图

REF

8-/10-/12-BIT

R-2R DAC

OUT

AD5426/

AD5432/

AD5443

DAC REGISTER

POWER-ON

RESET

INPUT LATCH

SYNC

SCLK

SDIN

CONTROL LOGIC AND

INPUT SHIFT REGISTER

SDO

03162-001

GND

图1.

美½专利第5,689,257号。

Rev. F

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Speci cations subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

www.analog.com

Tel: 781.329.4700

ADI中文版数据手册是英文版数据手册的译文，敬请谅解翻译中可½存在的语言组织或翻译错误，ADI不对翻译中存在的差异或由此产生的错误负责。如需确认任½词语的准确性，请参考ADI提供

的最新英文版数据手册。

AD5426/AD5432/AD5443

目½

特性..................................................................................................

应用..................................................................................................

概述..................................................................................................

功½框图

......................................................................................... 1

修订历史

......................................................................................... 2

技术规格

......................................................................................... 3

时序特性....................................................................................

绝对最大额定值............................................................................

ESD警告..................................................................................... 6

引脚配½和功½描述

................................................................... 7

典型性½参数

................................................................................ 8

术语................................................................................................

工½原理

....................................................................................... 15

电路工½原理

......................................................................... 15

单电源应用

............................................................................. 17

正输出电压

............................................................................. 17

加法增益..................................................................................

DAC用½分频器或可编程增益器件 ................................. 18

基准电压源选择.....................................................................

放大器选择

............................................................................. 18

串行接口..................................................................................

PCB布局和电源去耦.................................................................. 22

AD54xx和AD55xx器件概述 ..................................................... 23

外½尺寸

....................................................................................... 24

订购指南..................................................................................

修订历史

2012年7月—修订版E至修订版F

内容不变，仅更改7/12修订历史中的V

数值......................

2012年7月—修订版D至修订版E

将V

= 3 V改为V

= 2.5 V .................................................通篇

更改表2

........................................................................................... 4

更改表4

........................................................................................... 7

更改“菊花链模式”部分..............................................................

更改订购指南

.............................................................................. 24

2012年4月-修订版C至修订版D

将V

= 2.5 V改为V

= 3 V .................................................通篇

更改概述部分

................................................................................ 1

删除

“微

处理器接口

”部

分、

“ADSP-21xx与 AD5426/

AD5432/AD5443的接口”部分、图51、图52、表11、“ADSP-

BF5x与AD5426/AD5432/AD5443的接口”部分、图53、图54；

重新排序

....................................................................................... 21

删除“80C51/80L51与AD5426/AD5432/AD5443的接口”部

分、图55、“MC68HC11与AD5426/AD5432/AD5443的接

口”部分、图56、“MICROWIRE与AD5426/AD5432/AD5443

的接口”部分、图57、“PIC16C6x/7x与AD5426/AD5432/

AD5443的连接”部分以及图58................................................. 22

删除“AD5426/AD5432/AD5443系列DAC评估板”部分、“评

估板操½”部分、“电源”部分

................................................... 23

删除图59和图60

.......................................................................... 24

更新“外½尺寸”...........................................................................

更改“订购指南”...........................................................................

删除图61

....................................................................................... 25

删除图62

....................................................................................... 26

2009年2月—修订版B至修订版C

更改“½功耗串行接口”部分和“菊花链模式”部分

.............. 20

更新“外½尺寸”...........................................................................

2008年11月—修订版A至修订版B

更改“订购指南”...........................................................................

2005年5月—修订版0至修订版A

格式更新

...................................................................................通篇

更改技术规格

................................................................................ 3

更改图42

....................................................................................... 16

更改图45

....................................................................................... 17

更改图46

....................................................................................... 18

更改表7、表8和表9

................................................................... 19

新增“微处理器接口”部分

......................................................... 21

2004年2月—修订版0：初始版

Rev. F | Page 2 of 24

EVAL-AD5432EB Related Products

	EVAL-AD5432EB	AD5432	AD5432BRM	EVAL-AD5426EB	EVAL-AD5443EB	EVAL-AD5443EBZ	EVAL-AD5443-DBRDZ
Description	SERIAL INPUT LOADING, 0.09 us SETTLING TIME, 8-BIT DAC, PDSO10	SERIAL INPUT LOADING, 0.09 us SETTLING TIME, 8-BIT DAC, PDSO10	SERIAL INPUT LOADING, 0.035 us SETTLING TIME, 10-BIT DAC, PDSO10	SERIAL INPUT LOADING, 0.09 us SETTLING TIME, 8-BIT DAC, PDSO10	SERIAL INPUT LOADING, 0.09 us SETTLING TIME, 8-BIT DAC, PDSO10	EVAL BOARD FOR AD5443	EVAL BOARD FOR AD5443
Number of functions	1	1	1	1	1	-	-
Number of terminals	10	10	10	10	10	-	-
Maximum operating temperature	125 Cel	125 Cel	105 Cel	125 Cel	125 Cel	-	-
Minimum operating temperature	-40 Cel	-40 Cel	-40 Cel	-40 Cel	-40 Cel	-	-
Maximum linear error	0.0977 %	0.0977 %	0.0977 %	0.0977 %	0.0977 %	-	-
Processing package description	3 X 5 MM, MSOP-10	3 X 5 MM, MSOP-10	3 X 5 MM, MICRO, SOIC-10	3 X 5 MM, MSOP-10	3 X 5 MM, MSOP-10	-	-
state	EOL/LIFEBUY	EOL/LIFEBUY	DISCONTINUED	EOL/LIFEBUY	EOL/LIFEBUY	-	-
Craftsmanship	CMOS	CMOS	CMOS	CMOS	CMOS	-	-
packaging shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	-	-
Package Size	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	-	-
surface mount	Yes	Yes	Yes	Yes	Yes	-	-
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	-	-
Terminal spacing	0.5000 mm	0.5000 mm	0.5000 mm	0.5000 mm	0.5000 mm	-	-
terminal coating	TIN LEAD	TIN LEAD	TIN LEAD	TIN LEAD	TIN LEAD	-	-
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	-	-
Packaging Materials	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-	-
Temperature level	AUTOMOTIVE	AUTOMOTIVE	INDUSTRIAL	AUTOMOTIVE	AUTOMOTIVE	-	-
Input format	SERIAL	SERIAL	SERIAL	SERIAL	SERIAL	-	-
Type of converter	8-BIT DAC	8-BIT DAC	10-BIT DAC	8-BIT DAC	8-BIT DAC	-	-
Input bit encoding	BINARY	BINARY	BINARY	BINARY	BINARY	-	-
Rated settling time	0.0900 us	0.0900 us	0.0350 us	0.0900 us	0.0900 us	-	-
Maximum analog output voltage	5 V	5 V	-	5 V	5 V	-	-
Minimum analog output voltage	0.4000 V	0.4000 V	-	0.4000 V	0.4000 V	-	-

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