®
ISO
2
-CMOS
MT8870D/MT8870D-1
Integrated DTMF Receiver
Features
•
•
•
•
•
•
•
•
Complete DTMF Receiver
Low power consumption
Internal gain setting amplifier
Adjustable guard time
Central office quality
Power-down mode
Inhibit mode
Backward compatible with
MT8870C/MT8870C-1
ISSUE 3
May1995
Ordering Information
MT8870DE/DE-1 18 Pin Plastic DIP
MT8870DC/DC-1 18 Pin Ceramic DIP
MT8870DS/DS-1 18 Pin SOIC
MT8870DN/DN-1 20 Pin SSOP
MT8870DT/DT-1 20 Pin TSSOP
-40 °C to +85 °C
Description
The MT8870D/MT8870D-1 is a complete DTMF
receiver integrating both the bandsplit filter and
digital decoder functions. The filter section uses
switched capacitor techniques for high and low
group filters; the decoder uses digital counting
techniques to detect and decode all 16 DTMF tone-
pairs into a 4-bit code. External component count is
minimized by on chip provision of a differential input
amplifier, clock oscillator and latched three-state bus
interface.
Applications
•
•
•
•
•
•
•
Receiver system for British Telecom (BT) or
CEPT Spec (MT8870D-1)
Paging systems
Repeater systems/mobile radio
Credit card systems
Remote control
Personal computers
Telephone answering machine
VDD
VSS
VRef
INH
PWDN
Bias
Circuit
VRef
Buffer
Q1
Chip Chip
Power Bias
IN +
IN -
GS
Dial
Tone
Filter
High Group
Filter
Zero Crossing
Detectors
Low Group
Filter
Digital
Detection
Algorithm
Code
Converter
and Latch
Q2
Q3
Q4
to all
Chip
Clocks
St
GT
Steering
Logic
OSC1
OSC2
St/GT
ESt
STD
TOE
Figure 1 - Functional Block Diagram
4-11
MT8870D/MT8870D-1
IN+
IN-
GS
VRef
INH
PWDN
OSC1
OSC2
VSS
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
ISO
2
-CMOS
VDD
St/GT
ESt
StD
Q4
Q3
Q2
Q1
TOE
IN+
IN-
GS
VRef
INH
PWDN
NC
OSC1
OSC2
VSS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VDD
St/GT
ESt
StD
NC
Q4
Q3
Q2
Q1
TOE
18 PIN CERDIP/PLASTIC DIP/SOIC
20 PIN SSOP/TSSOP
Figure 2 - Pin Connections
Pin Description
Pin #
18
1
2
3
4
5
6
7
8
9
10
20
1
2
3
4
5
6
8
9
10
11
Name
IN+
IN-
GS
V
Ref
INH
PWDN
OSC1
OSC2
V
SS
TOE
Q1-Q4
Non-Inverting Op-Amp (Input).
Inverting Op-Amp (Input).
Gain Select.
Gives access to output of front end differential amplifier for connection of
feedback resistor.
Reference Voltage (Output).
Nominally V
DD
/2 is used to bias inputs at mid-rail (see Fig. 6
and Fig. 10).
Inhibit (Input).
Logic high inhibits the detection of tones representing characters A, B, C
and D. This pin input is internally pulled down.
Power Down (Input).
Active high. Powers down the device and inhibits the oscillator. This
pin input is internally pulled down.
Clock (Input).
Clock (Output).
A 3.579545 MHz crystal connected between pins OSC1 and OSC2
completes the internal oscillator circuit.
Ground (Input).
0V typical.
Three State Output Enable (Input).
Logic high enables the outputs Q1-Q4. This pin is
pulled up internally.
Three State Data (Output).
When enabled by TOE, provide the code corresponding to the
last valid tone-pair received (see Table 1). When TOE is logic low, the data outputs are high
impedance.
Delayed Steering (Output).Presents
a logic high when a received tone-pair has been
registered and the output latch updated; returns to logic low when the voltage on St/GT falls
below V
TSt
.
Early Steering (Output).
Presents a logic high once the digital algorithm has detected a
valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt to
return to a logic low.
Steering Input/Guard time (Output) Bidirectional.
A voltage greater than V
TSt
detected at
St causes the device to register the detected tone pair and update the output latch. A
voltage less than V
TSt
frees the device to accept a new tone pair. The GT output acts to
reset the external steering time-constant; its state is a function of ESt and the voltage on St.
Positive power supply (Input).
+5V typical.
No Connection.
Description
11- 12-
14 15
15
17
StD
16
18
ESt
17
19
St/GT
18
20
7,
16
V
DD
NC
4-12
ISO
2
-CMOS
Functional Description
V
DD
MT8870D/MT8870D-1
The
MT8870D/MT8870D-1
monolithic
DTMF
receiver offers small size, low power consumption
and high performance. Its architecture consists of a
bandsplit filter section, which separates the high and
low group tones, followed by a digital counting
section which verifies the frequency and duration of
the received tones before passing the corresponding
code to the output bus.
Filter Section
Separation of the low-group and high group tones is
achieved by applying the DTMF signal to the inputs
of two sixth-order switched capacitor bandpass
filters, the bandwidths of which correspond to the low
and high group frequencies. The filter section also
incorporates notches at 350 and 440 Hz for
exceptional dial tone rejection (see Figure 3). Each
filter output is followed by a single order switched
capacitor filter section which smooths the signals
prior to limiting. Limiting is performed by high-gain
comparators which are provided with hysteresis to
prevent detection of unwanted low-level signals. The
outputs of the comparators provide full rail logic
swings at the frequencies of the incoming DTMF
signals.
Decoder Section
Following the filter section is a decoder employing
digital counting techniques to determine the
frequencies of the incoming tones and to verify that
they correspond to standard DTMF frequencies. A
complex averaging algorithm protects against tone
simulation by extraneous signals such as voice while
0
V
DD
St/GT
ESt
R
StD
MT8870D/
MT8870D-1
C
v
c
t
GTA
=(RC)In(V
DD
/V
TSt
)
t
GTP
=(RC)In[V
DD
/(V
DD
-V
TSt
)]
Figure 4 - Basic Steering Circuit
providing tolerance to small frequency deviations
and variations. This averaging algorithm has been
developed to ensure an optimum combination of
immunity to talk-off and tolerance to the presence of
interfering frequencies (third tones) and noise. When
the detector recognizes the presence of two valid
tones (this is referred to as the “signal condition” in
some industry specifications) the “Early Steering”
(ESt) output will go to an active state. Any
subsequent loss of signal condition will cause ESt to
assume an inactive state (see “Steering Circuit”).
Steering Circuit
Before registration of a decoded tone pair, the
receiver checks for a valid signal duration (referred
to as character recognition condition). This check is
performed by an external RC time constant driven by
ESt. A logic high on ESt causes v
c
(see Figure 4) to
rise as the capacitor discharges. Provided signal
PRECISE
DIAL TONES
X=350 Hz
Y=440 Hz
DTMF TONES
A=697 Hz
B=770 Hz
C=852 Hz
D=941 Hz
E=1209 Hz
F=1336 Hz
G=1477 Hz
H=1633 Hz
10
20
ATTENUATION
(dB)
30
40
50
AAAA
AA
AA A
A
AA
AAA AAAAAAAAAAAAAAAAAA AA
AA
AAAA
A
AAAAA
AAAA
AAAAA
AAAA AAAAAAAAAAAAAAAAAAAAAA
AAA
AAA
AA
A
AA
AAAAAAAAA
AAA
AA
AA
AAAAAAA
AA AAAA
AA AAA
AAA
AA
AA
AAA
AAA
AA
AA
AAAAA
AAAAAA
AAA
AAAA
AAA
AA
AAAAAAA
AAA
AA AA
AAA
AAA
AAA
AA
A
AAAAA
AAAAAA
AAA
AA
AAA
AAA
AA
AAA
AAAA
AA
AAA
AAA
AA
A
AA
AA
AA
AA
AAA
AA
AAA
AA
AA
AA
AAA
AA
AAA
AA
AA
AA
AAA
AA
AAA
AA
AA
AAA
AA
AA
AA
AAA
AA
AAA
AAA
AA
A
AA
AA
AA
AA
AAAA
AAA
AA
AAAAAAAA
AAAAAAA AA
AAAAAAA AAA
AAAAAAA AAA AA
AAAAAAAAAA
AA A AAAA AAA
AA
A
AAAAA
AAA
AA
AA
AAA AA
AAA
AA AA
AAA
AAA
AAA
AA AA
AA
AAA
AAAA
AA
AAA
A
AAAAA
AAAAA
AA
AAA
AAA
AA
AAAAA
AAAAA
AA
AAA
AA
AA
AAA
AA
AAA
AAA
AA
A
AAA
AA
AAA
AA
AAA
AAA
AA
AAA
AA
AAA
AAA
AA
A
AA
AA
AA
1kHz
X
Y
A B
C
D
E
F
G
H
FREQUENCY (Hz)
Figure 3 - Filter Response
4-13
MT8870D/MT8870D-1
ISO
2
-CMOS
Digit
ANY
1
2
3
4
5
6
7
8
9
0
*
#
A
B
C
D
A
TOE
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
INH
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
H
H
H
H
ESt
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
undetected, the output code
will remain the same as the
previous detected code
Q
4
Z
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
Q
3
Z
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
Q
2
Z
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
Q
1
Z
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
condition is maintained (ESt remains high) for the
validation period (t
GTP
), v
c
reaches the threshold
(V
TSt
) of the steering logic to register the tone pair,
latching its corresponding 4-bit code (see Table 1)
into the output latch. At this point the GT output is
activated and drives v
c
to V
DD
. GT continues to drive
high as long as ESt remains high. Finally, after a
short delay to allow the output latch to settle, the
delayed steering output flag (StD) goes high,
signalling that a received tone pair has been
registered. The contents of the output latch are made
available on the 4-bit output bus by raising the three
state control input (TOE) to a logic high. The
steering circuit works in reverse to validate the
interdigit pause between signals. Thus, as well as
rejecting signals too short to be considered valid, the
receiver will tolerate signal interruptions (dropout)
too short to be considered a valid pause. This facility,
together with the capability of selecting the steering
time constants externally, allows the designer to
tailor performance to meet a wide variety of system
requirements.
Guard Time Adjustment
In many situations not requiring selection of tone
duration and interdigital pause, the simple steering
circuit shown in Figure 4 is applicable. Component
values are chosen according to the formula:
B
C
D
Table 1. Functional Decode Table
L=LOGIC LOW, H=LOGIC HIGH, Z=HIGH IMPEDANCE
X = DON‘T CARE
t
REC
=t
DP
+t
GTP
t
ID
=t
DA
+t
GTA
The value of t
DP
is a device parameter (see Figure
11) and t
REC
is the minimum signal duration to be
recognized by the receiver. A value for C of 0.1 µF is
t
GTP
=(R
P
C
1
)In[V
DD
/(V
DD
-V
TSt
)]
V
DD
C
1
St/GT
R
1
ESt
R
2
recommended for most applications, leaving R to be
selected by the designer.
Different steering arrangements may be used to
select independently the guard times for tone
present (t
GTP
) and tone absent (t
GTA
). This may be
necessary to meet system specifications which place
both accept and reject limits on both tone duration
and interdigital pause. Guard time adjustment also
allows the designer to tailor system parameters
such as talk off and noise immunity. Increasing t
REC
improves talk-off performance since it reduces the
probability that tones simulated by speech will
maintain signal condition long enough to be
registered. Alternatively, a relatively short t
REC
with
a long t
DO
would be appropriate for extremely noisy
environments where fast acquisition time and
immunity to tone drop-outs are required. Design
information for guard time adjustment is shown in
Figure 5.
t
GTA
=(R
1
C
1
)In(V
DD
/V
TSt
)
R
P
=(R
1
R
2
)/(R
1
+R
2
)
a) decreasing t
GTP
; (t
GTP
<t
GTA
)
t
GTP
=(R
1
C
1
)In[V
DD
/(V
DD
-V
TSt
)]
V
DD
C
1
St/GT
R
2
t
GTA
=(R
P
C
1
)In(V
DD
/V
TSt
)
R
P
=(R
1
R
2
)/(R
1
+R
2
)
R
1
ESt
b) decreasing t
GTA
; (t
GTP
>t
GTA
)
Figure 5 - Guard Time Adjustment
4-14
ISO
2
-CMOS
Power-down and Inhibit Mode
A logic high applied to pin 6 (PWDN) will power down
the device to minimize the power consumption in a
standby mode. It stops the oscillator and the
functions of the filters.
Inhibit mode is enabled by a logic high input to the
pin 5 (INH). It inhibits the detection of tones
representing characters A, B, C, and D. The output
code will remain the same as the previous detected
code (see Table 1).
Differential Input Configuration
The input arrangement of the MT8870D/MT8870D-1
provides a differential-input operational amplifier as
well as a bias source (V
Ref
) which is used to bias the
inputs at mid-rail. Provision is made for connection of
a feedback resistor to the op-amp output (GS) for
adjustment of gain. In a single-ended configuration,
the input pins are connected as shown in Figure 10
with the op-amp connected for unity gain and V
Ref
biasing the input at
1
/
2
V
DD
. Figure 6 shows the
differential configuration, which permits the
adjustment of gain with the feedback resistor R
5
.
Crystal Oscillator
MT8870D/MT8870D-1
C
1
R
1
IN+
MT8870D/
MT8870D-1
+
-
IN-
C
2
R
4
R
5
R
3
GS
R
2
V
Ref
Differential Input Amplifier
C
1
=C
2
=10 nF
R
1
=R
4
=R
5
=100 kΩ
All resistors are
±1%
tolerance.
R
2
=60kΩ, R
3
=37.5 kΩ
All capacitors are
±5%
tolerance.
R
3
=
R
2
R
5
R
2
+R
5
R
5
R
1
VOLTAGE GAIN (A
v
diff)=
INPUT IMPEDANCE
(Z
INDIFF
) = 2
R
1 2
+
1
ωc
2
Figure 6 - Differential Input Configuration
The internal clock circuit is completed with the
addition of an external 3.579545 MHz crystal and is
normally connected as shown in Figure 10 (Single-
Ended Input Configuration). However, it is possible
to configure several MT8870D/MT8870D-1 devices
employing only a single oscillator crystal. The
oscillator output of the first device in the chain is
coupled through a 30 pF capacitor to the oscillator
input (OSC1) of the next device. Subsequent devices
are connected in a similar fashion. Refer to Figure 7
for details. The problems associated with
unbalanced loading are not a concern with the
arrangement shown, i.e., precision balancing
capacitors are not required.
C
X-tal
OSC1
OSC2
To OSC1 of next
MT8870D/MT8870D-1
OSC2
C
OSC1
C=30 pF
X-tal=3.579545 MHz
Figure 7 - Oscillator Connection
Parameter
R1
L1
C1
C0
Qm
∆f
Unit
Ohms
mH
pF
pF
-
%
Resonator
10.752
.432
4.984
37.915
896.37
±0.2%
Table 2. Recommended Resonator Specifications
Note: Qm=quality factor of RLC model, i.e., 1/2ΠƒR1C1.
4-15
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