FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243
FlexQ
TM
III
3.3 Volt Synchronous x9/x18 First-In/First-Out Queue
Memory Organization
262,144 x 18 / 524,288 x 9
131,072 x 18 / 262,144 x 9
65,536 x 18 / 131,072 x 9
32,768 x 18 / 65,536 x 9
Device
FQV2113
FQV2103
FQV293
FQV283
Memory Organization
16,384 x 18 / 32,768 x 9
8,192 x 18 / 16,384 x 9
4,096 x 18 / 8,192 x 9
2,048 x 18 / 4,096 x 9
Device
FQV273
FQV263
FQV253
FQV243
Key Features
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Industry leading First-In/First-Out Queues (up to 166MHz)
Write cycle time of 6.0ns independent of Read cycle time (Data Setup time = 2.0ns)
Read cycle time of 6.0ns independent of Write cycle time (Data Access time = 4.0ns)
User selectable input and output port bus-sizing
Big Endian/Little Endian user selectable byte representation
3.3V power supply
5V input tolerant on all control and data input pins
5V output tolerant on all flags and data output pins
Master Reset clears all previously programmed configurations including Write and Read pointers
Partial Reset clears Write and Read pointers but maintains all previously programmed configurations
First Word Fall Through (FWFT) and Standard Timing modes
Presets for eight different Almost Full and Almost Empty offset values
Parallel/Serial programming of
PRAF and PRAE offset values
Programmable 8-bit or 9-bit parallel programming modes for offset values
Full, Empty, Almost Full, Almost Empty, and Half Full indicators
PRAF and PRAE operates in either synchronous or asynchronous modes
Asynchronous output enable tri-state data output drivers
Data retransmission with programmable zero or normal latency modes
Available package: 80 - pin Plastic Thin Quad Flat Pack (TQFP)
(0°C to 70°C) Commercial operating temperature available for cycle time of 6.0ns and above
(-40°C to 85°C) Industrial operating temperature available for cycle time of 7.5ns and above
Product Description
HBA’s FlexQ™ III offers industry leading FIFO queuing bandwidth (up to 3.0 Gbps), with a wide range of memory
configurations (from 2,048 x 18 to 262,144 x 18 or 4,096 x 9 to 524,286 x 9). System designer has full flexibility of
implementing deeper and wider queues using FWFT mode and width expansion features. Full, Empty, and Half-Full indicators
allow easy handshaking between transmitters and receivers. User programmable Almost Full and Almost Empty (Parallel/Serial)
indicators allow implementation of virtual queue depths.
5V tolerant on all input and output pins allows easy interfacing with devices operating at higher voltage levels. Asynchronous
Output Enable pin configures the tri-state data output drivers. Independent Write and Read controls provide rate-matching
capability.
Master Reset clears all previously programmed configurations by providing a low pulse on
MRST pin. In addition, Write and
Read pointers to the queue are initialized to zero. Partial Reset will not alter previously programmed configurations but will
initialize Write and Read pointers to zero.
In FWFT mode, the first data written into the queue appears on output data bus after the specified latency period at the low to
high transition of RCLK. Subsequent reads from the queue will require asserting
REN
. This feature is useful when
implementing depth expansion functions. In this mode, DRDY and QRDY are used instead of
FULL
and
EMPTY respectively.
3F30918C
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
JANUARY 2003
Page 1 of 43
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243
FlexQ
TM
III
Product Description (Continued)
In Standard mode, always assert
REN
whenever a read operation.
FULL
and EMPTY are used instead of DRDY and
QRDY respectively.
Bus matching feature is available with the following configurations:
Input Bus Width
x9
x9
x18
x18
Output Bus Width
x9
x18
x9
x18
In addition, Endian Select is available for implementing byte re-ordering on data outputs.
Eight different default offset values are available for Almost Full ( PRAF ) and Almost Empty ( PRAE ) flags. Parallel and Serial
programming of these offset values provide total flexibility other than the pre-defined default values. Both 8-bit and 9-bit
parallel programming modes for offset values can be selected for convenience.
PRAF , PRAE , and HALF are available in either FWFT or Standard mode. PRAF and PRAE can operate in either
synchronous or asynchronous modes.
At any time, data previously read from the queue can be retransmitted by asserting RET pin at the low to high transition of
RCLK for a retransmit operation. Retransmit initializes the Read pointer to zero. Hence, all re-reads will always start from the
physical 0
th
(Read pointer = zero) location of the queue. Both zero and normal latency timing modes are available for retransmit
operation.
These FlexQ™ III devices have low power consumption, hence minimizing system power requirements. In addition, industry
standard 80 - pin Plastic TQFP is offered to save system board space.
These queues are ideal for applications such as data communication, telecommunication, graphics, multiprocessing, test
equipment, network switching, etc.
.
3F30918C
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
JANUARY 2003
Page 2 of 43
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243
FlexQ
TM
III
Block Diagram of Single Synchronous Queue
262,144 x 18 / 131,072 x 18 / 65,536 x 18 / 32,768 x 18 / 16,384 x 18 / 8,192 x 18 / 4,096 x 18 / 2,048 x 18 /
524,288 x 9 / 262,144 x 9 / 131,072 X 9 / 65,536 X 9 / 32,768 X 9 / 16,384 X 9 / 8,192 x 9 / 4,096 x 9
PARTIAL RESET ( PRST )
MASTER RESET ( MRST)
READ CLOCK (RCLK)
WRTIE CLOCK (WCLK)
WRITE ENABLE ( WEN)
LOAD ( LOAD)
x18 or x9 DATA IN (D
17 - 0
)
SERIAL DATA ENABLE
( SDEN )
FIRST WORD FALL THROUGH/
SERIAL DATA INPUT (FWFT/SDI)
FULL FLAG / INPUT READY
( FULL / DRDY )
PROGRAMMABLE
ALMOST-FULL (
PRAF
)
FQV2113
FQV2103
FQV293
FQV283
FQV273
FQV263
FQV253
FQV243
READ ENABLE ( REN )
OUTPUT ENABLE ( OE )
x18 or x9 DATA OUT (Q
17 - 0
)
RETRANSMIT ( RET)
EMPTY FLAG / OUTPUT READY
(
EMPTY / QRDY
)
PROGRAMMABLE ALMOST-
EMPTY ( PRAE )
HALF-FULL FLAG (
HALF
)
BIG-ENDIAN / LITTLE-ENDIAN (
ES
)
INTERSPERSED /
NON-INTERSPERSED PARITY (IPAR)
BUS MATCHING 1
(BM1)
BUS MATCHING 0
(BM0)
Figure 1. Single Device Configuration Signal Flow Diagram
3F30918C
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
JANUARY 2003
Page 3 of 43
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