FT6164L-25DWM datasheet, PDF - EEWORLD Datasheet

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FT6164L-25DWM: DescriptionStandard SRAM, 8KX8, 25ns, CMOS, CDIP28, 0.600 INCH, CERDIP-28; Categorystorage storage; File Size361KB，17 Pages; ManufacturerForce Technologies Ltd.

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FT6164L-25DWM Overview

Standard SRAM, 8KX8, 25ns, CMOS, CDIP28, 0.600 INCH, CERDIP-28

FT6164L-25DWM Parametric

Parameter Name	Attribute value
Maker	Force Technologies Ltd.
Parts packaging code	DIP
package instruction	DIP,
Contacts	28
Reach Compliance Code	compliant
ECCN code	3A001.A.2.C
Maximum access time	25 ns
JESD-30 code	R-GDIP-T28
memory density	65536 bit
Memory IC Type	STANDARD SRAM
memory width	8
Number of functions	1
Number of terminals	28
word count	8192 words
character code	8000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	8KX8
Package body material	CERAMIC, GLASS-SEALED
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Parallel/Serial	PARALLEL
Maximum seat height	5.8928 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
width	15.24 mm
Base Number Matches	1

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FT6164

FEATURES

Full CMOS, 6T Cell

High Speed (Equal Access and Cycle Times)

– 8/10/12/15/20/25/35/70/100 ns (Commercial)

– 10/12/15/20/25/35/70/100 ns(Industrial)

– 12/15/20/25/35/45/70/100 ns (Military)

Low Power Operation

Output Enable and Dual Chip Enable Control

Functions

Single 5V±10% Power Supply

Data Retention with 2.0V Supply, 10 µA Typical

Current (FT6164L Military)

ULTRA HIGH SPEED 8K x 8

STATIC CMOS RAMS

Common Data I/O

Fully TTL Compatible Inputs and Outputs

Standard Pinout (JEDEC Approved)

– 28-Pin 300 mil Plastic DIP, SOJ

– 28-Pin 600 mil Plastic DIP (70 & 100ns)

– 28-Pin 300 mil SOP (70 & 100ns)

– 28-Pin 300 mil Ceramic DIP

– 28-Pin 600 mil Ceramic DIP

– 28-Pin 350 x 550 mil LCC

– 32-Pin 450 x 550 mil LCC

– 28-Pin CERPACK

DESCRIPTION

The FT6164 is a 65,536-bit ultra high-speed static RAM

organised as 8K x 8. The CMOS memory requires no

clocks or refreshing and has equal access and cycle

times. Inputs are fully TTL-compatible. The RAM operates

from a single 5V±10% tolerance power supply. With

battery backup, data integrity is maintained with supply

voltages down to 2.0V. Current drain is typically 10 µA

from a 2.0V supply.

Access times as fast as 8 nanoseconds are available,

permitting greatly enhanced system operating speeds.

The FT6164 is available in 28-pin 300 mil DIP and SOJ, 28-

pin 600 mil plastic and ceramic DIP, 28-pin 350 x 550 mil

LCC, 32-pin 450 x 550 mil LCC, and 28-pin CERPACK.

The 70ns and 100ns FT6164s are available in the 600 mil

plastic DIP.

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATIONS

DIP (P5, P6, C5, C5-1, D5-1, D5-2),

SOJ (J5), CERPACK (F4), SOP(S6)

SEE PAGE 7 FOR LCC PIN CONFIGURATIONS

1519B

REV 1.6

1 of 17

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